Device and method for requesting an analog-to-digital conversion

Patent metadata

Field	Value
Publication number	US-10181859-B2
Application number	US-201815895453-A
Country	US
Kind code	B2
Filing date	Feb 13, 2018
Priority date	Feb 14, 2017
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

An Analog-to-Digital-Conversion control system includes a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter, which comprises a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit, wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.

First claim

The invention claimed is:

1. A method, comprising:
receiving sampling trigger information to trigger sampling performed by a sample and hold stage which is configured to generate a sampled output;
receiving status information to determine whether a corresponding Analog-to-Digital-Converter is ready to convert the sampled output;
if the status information indicates that the corresponding Analog-to-Digital-Converter is ready to convert the sampled output, sampling an analog input by the sample and hold stage during a sampling time; and
if the sampling fulfills predefined sampling criteria, requesting conversion to be performed by the Analog-to-Digital-Converter.

2. The method of claim 1 , wherein the predefined sampling criteria comprise a minimum sampling time.

3. The method of claim 1 , wherein the predefined sampling criteria comprise that the sampling occurred in a valid time window.

4. The method of claim 1 , wherein the sampling trigger information is generated by a requester.

5. The method of claim 1 , further comprising providing a timestamp indicating the sampling time.

6. A device, comprising:
a first sample and hold circuit configured to provide a first sampled output to be converted by an Analog-to-Digital-Converter comprising:
a first sampling control circuit configured to receive a first trigger information to trigger sampling of a first analog input, and to receive a first collision detection information from the Analog-to-Digital-Converter to detect a collision, and
a first sample and hold stage coupled to the first sampling control circuit and configured to sample the first analog input, only if no collision has been detected by the first sampling control circuit,

wherein the first sampling control circuit is further configured to check predefined first sampling criteria and to output a first conversion request to the Analog-to-Digital-Converter, only if the predefined first sampling criteria are fulfilled.

7. The device of claim 6 , wherein the predefined first sampling criteria comprise a minimum sampling time.

8. The device of claim 6 , wherein the predefined first sampling criteria comprise that the sampling occurred in a valid time window.

9. The device of claim 6 , wherein the first sample control circuit is further configured to provide a first timestamp indicating a time of sampling.

10. The device of claim 9 , wherein the predefined first sampling criteria comprise an outdated first timestamp.

11. The device of claim 6 , further comprising:
an Analog-to-Digital-Converter configured to receive the first sampled output and to convert the first sampled output into an output value if a conversion is requested.

12. The device of claim 11 , wherein the Analog-to-Digital-Converter comprises:
an Analog-to-Digital-Conversion control circuit configured to receive the first conversion request, to provide the first collision detection information to indicate whether a collision is detected, and to provide a selected sampled output; and
an Analog-to-Digital-Conversion circuit configured to convert the selected sampled output into a digital value.

13. An Analog-to-Digital-Conversion (ADC) system, comprising:
a device according to claim 11 , further comprising:
a second sample and hold circuit configured to provide a second sampled output to be converted by the Analog-to-Digital-Converter comprising:
a second sampling control circuit configured to receive a second trigger information to trigger sampling of a second analog input, and to receive a second collision detection information from the corresponding Analog-to-Digital-Converter to detect a collision; and
a second sample and hold stage coupled to the second sampling control circuit and configured to sample the second analog input, only if no collision has been detected by the second sampling control circuit,

wherein the second sampling control circuit is further configured to check predefined second sampling criteria, and to output a second conversion request to the Analog-to-Digital-Converter, only if the predefined second sampling criteria are fulfilled.

14. The ADC conversion system of claim 13 , wherein the Analog-to-Digital-Converter comprises:
an Analog-to-Digital-Conversion control circuit configured to receive the second conversion request, to provide the second collision detection information, and to select one of the first and second conversion requests according to a predefined arbitration scheme.

15. The ADC conversion system of claim 14 ,
wherein the Analog-to-Digital-Conversion control circuit is further configured to receive a status message from the Analog-to-Digital-Conversion circuit,
wherein the status message comprises information about an operating mode of the Analog-to-Digital-Conversion circuit, and
wherein the Analog-to-Digital-Conversion control circuit is further configured to activate a starting signal to start conversion of a sampled output signal if the Analog-to-Digital-Conversion circuit is not in conversion mode.

16. The ADC conversion system of claim 14 , further comprising:
a multiplexer configured to select one of the plurality of sampled output signals to be controlled by the Analog-to-Digital-Conversion control circuit.

17. The ADC conversion system of claim 13 ,
wherein the first sample control circuit is further configured to provide a first timestamp,
wherein the second sample control circuit is further configured to provide a second timestamp, and
wherein Analog-to-Digital-Conversion control circuit is further configured to receive the first and second timestamp for further processing.

18. The ADC conversion system of claim 17 ,
wherein the first timestamp denotes the end of a first sampling interval, and the second timestamp denotes the end of a second sampling interval.

19. The ADC conversion system of claim 17 further comprising:
a memory configured to store the first or second timestamp in addition to the digital output signal.

20. The ADC conversion system of claim 17 ,
wherein the Analog-to-Digital-Conversion control circuit is configured to measure a current time value, to generate a time difference value based on the current time value and the first or second timestamp, and to store the digital output signal if the time difference value is smaller than a predefined threshold.

Assignees

• Infineon Technologies Ag

Inventors

• Barrenscheen Jens
• Bogner Peter
• Schaefer Juergen

Classifications

• H02P27/06

  using DC to AC converters or inverters (H02P27/05 takes precedence) · CPC title

• H03M1/122

  Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title

• H03M1/0624

  by synchronisation · CPC title

• H02M3/33546

  with automatic control of the output voltage or current (H02M3/33561 takes precedence) · CPC title