Selective writes in a storage element

US10181350B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10181350-B2
Application numberUS-201715842207-A
CountryUS
Kind codeB2
Filing dateDec 14, 2017
Priority dateOct 26, 2016
Publication dateJan 15, 2019
Grant dateJan 15, 2019

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  1. Title

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  2. Abstract

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are different.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of writing a state to a correlated electron element in a storage circuit, the method comprising receiving a write command for writing the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver for writing the state into the correlated electron element when the state and read state are different wherein the reading of the stored state is read on a bitline coupled across a sense amplifier and the correlated electron element. 2. A method as claimed in claim 1 , wherein enabling the write driver includes resetting from a high-impedance state to a low impedance state or setting from a low-impedance state to a high impedance state. 3. A method as claimed in claim 1 , wherein the bitline is pulled down to a reference voltage when the state and the read state are the same. 4. A method as claimed in claim 1 , wherein the bitline is pulled up to a reference voltage when the state and read state are different. 5. A method as claimed in claim 1 , wherein reading occurs in a read-pulse where write is inactive. 6. A method as claimed in claim 1 , wherein writing occurs in a write-pulse where reading is not active. 7. A method as claimed in claim 6 , wherein the read and write pulses are done in separate clock cycles. 8. A method as claimed in claim 6 , wherein the read and write pulses are done in a single clock cycle. 9. A method as claimed in claim 8 , wherein the clock is a timing pulse to make a pulsed read. 10. A method as claimed in claim 9 , wherein the clock is a timing pulse to make a pulsed read. 11. A method as claimed in claim 1 , including in the event of the stored state and read state being matching states, not writing the state to be written into the correlated electron element. 12. A method as claimed in claim 11 , wherein the not writing the state to be written into the correlated electron element occurs in a second clock cycle, following a first clock cycle comprising reading the stored state. 13. A method as claimed in claim 1 , wherein the state of the correlated electron element is controllable by the write driver to be in one of a high impedance state and a low impedance state. 14. A method of saving data to a hard disk as claimed in claim 1 .

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Classifications

  • Material having complex metal oxide, e.g. perovskite structure · CPC title

  • Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title

  • Write conditionally, e.g. only if new data and old data differ · CPC title

  • Writing or programming circuits or methods · CPC title

  • comprising metal oxide memory material, e.g. perovskites · CPC title

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What does patent US10181350B2 cover?
A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are d…
Who is the assignee on this patent?
Advanced Risc Mach Ltd
What technology area does this patent fall under?
Primary CPC classification G11C13/0069. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 15 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).