Apparatus for information processing with loop cache and associated methods

Patent metadata

Field	Value
Publication number	US-10180839-B2
Application number	US-201615061018-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	Mar 4, 2016
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

An apparatus includes a processor and a loop cache coupled to the processor. The loop cache provides to the processor instructions corresponding to a loop in the instructions. The loop cache includes a persistence counter.

First claim

The invention claimed is:

1. An apparatus comprising:
a processor to execute instructions; and
a loop cache coupled to the processor to provide to the processor instructions corresponding to a loop in the instructions, the loop cache comprising a persistence counter, wherein the persistence counter uses a number of times a branch identifying event is ignored before replacement of contents of the loop cache occurs.

2. The apparatus according to claim 1 , wherein the persistence counter has a corresponding count value, and wherein contents of the loop cache are replaced when the count value reaches zero.

3. The apparatus according to claim 1 , wherein the persistence counter starts counting from an initial persistence factor.

4. The apparatus according to claim 3 , wherein the persistence counter counts down depending on whether a loop cache miss occurs.

5. The apparatus according to claim 1 , wherein the loop cache is filled with instructions corresponding to a loop when existence of a loop within the instructions is determined.

6. The apparatus according to claim 5 , wherein the existence of the loop within the instructions is determined by the processor.

7. The apparatus according to claim 5 , wherein the existence of the loop within the instructions is determined by at least one flag included in the instructions.

8. The apparatus according to claim 3 , wherein the persistence factor is static during execution of the instructions.

9. The apparatus according to claim 3 , wherein the persistence factor is changed dynamically during execution of the instructions.

10. The apparatus according to claim 3 , wherein the persistence factor is determined empirically.

11. A microcontroller unit (MCU) comprising:
a processor to receive and execute a set of instructions;
a loop cache, comprising:
a storage circuit to store instructions corresponding to a loop in the set of instructions; and
a persistence counter to count down from a persistence factor, wherein the persistence counter uses a number of times a branch identifying event is ignored before replacement of contents of the loop cache occurs.

12. The MCU according to claim 11 , wherein the storage circuit comprises a buffer.

13. The MCU according to claim 11 , wherein the loop cache further comprises a control circuit coupled to the processor and to the loop cache to facilitate transfer of information between the processor and the loop cache.

14. The MCU according to claim 11 , wherein the persistence counter counts down depending on whether a loop cache miss occurs.

15. The MCU according to claim 11 , further comprising at least one of a main memory and a cache to provide instructions corresponding to the loop in the set of instructions in the event of a loop cache miss.

16. A method of processing information, the method comprising:
executing instructions using a processor;
using a loop cache to provide to the processor instructions corresponding to a loop in the instructions by using a persistence counter, wherein the persistence counter uses a number of times a branch identifying event is ignored before replacement of contents of the loop cache occurs.

17. The method according to claim 16 , further comprising counting down, using the persistence counter, from a persistence factor.

18. The method according to claim 17 , wherein counting down, using the persistence counter, from the persistence factor further comprises counting down depending on whether a loop cache miss occurs.

19. The method according to claim 17 , further comprising using a static persistence factor.

20. The method according to claim 17 , further comprising using a dynamic persistence factor.

Assignees

• Silicon Lab Inc

Inventors

• Johnson Mark W
• Zavalney Paul
• Grannaes Marius
• Loe Oeivind A G

Classifications

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/30065

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F9/325

  for loops, e.g. loop detection or loop counter · CPC title

• G06F9/30047 Primary

  Prefetch instructions; cache control instructions · CPC title