Systems and methods for power optimization of processors

US10180828B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10180828-B2
Application numberUS-201514699876-A
CountryUS
Kind codeB2
Filing dateApr 29, 2015
Priority dateApr 29, 2014
Publication dateJan 15, 2019
Grant dateJan 15, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A compilation system generates one or more energy windows in a program to be executed on a data processors such that power/energy consumption of the data processor can be adjusted in which window, so as to minimize the overall power/energy consumption of the data processor during the execution of the program. The size(s) of the energy window(s) and/or power option(s) in each window can be determined according to one or more parameters of the data processor and/or one or more characteristics of the energy window(s).

First claim

Opening claim text (preview).

Accordingly, we claim: 1. A method for optimizing energy consumption of a data processor while executing a program, the method comprising performing by a compilation processor the steps of: generating within the program a first window; determining window type of the first window; and inserting a power control operation in the first window based on, at least in part, energy consumed by operations in the first window, the energy consumed being computed using: at least one parameter of at least one component of the data processor, at least one characteristic of the first window, and the window type of the first window; wherein the window type of the first window is computation bound window or memory bound window; and when the window type of the first window is computation bound window the power control operation changes an operating voltage of a CPU of the data processor from a first value to a second value greater than the first value only if a parameter related to compute operations is not less than a function of a transition latency associated with transitioning operation of the CPU from a first CPU frequency to a second CPU frequency greater than the first CPU frequency; and when the window type of the first window is memory bound window the power control operation changes an operating voltage of a CPU of the data processor from a second value to a first value less than the second value only if a parameter related to memory operations is not less than a function of a transition latency associated with transitioning operation of the data processor from a second CPU frequency to a first CPU frequency less than the second frequency. 2. The method of claim 1 , wherein generating the first window comprises generating a window of a particular size, the particular size being determined as a function of a transition latency associated with transitioning operation of a component of data processor from a first component-operating frequency to a second-component operating frequency different from the first component-operating frequency. 3. The method of claim 1 , wherein: the first window comprises at least one group comprising a sequence of statements of the program; and generating the first window comprises: analyzing a representation of the program in a particular format; and forming, using that format, the at least one group, at a granularity based on, at least in part, at least one parameter of at least one component of the data processor. 4. The method of claim 1 , wherein determining the window type of the first window comprises: computing a number of computation operations associated with the first window; computing a number of memory operations associated with the first window; computing arithmetic intensity of the first window as a function of the number of computation operations and the number of memory operations; and setting the window type to memory bound window if the arithmetic intensity is less than a threshold and otherwise setting the window type to computation bound window. 5. The method of claim 1 , wherein determining the window type of the first window comprises inserting in the first window: an expression to compute at runtime a number of computation operations associated with the first window; an expression to compute at runtime a number of memory operations associated with the first window; an expression to compute at runtime an arithmetic intensity of the first window as a function of the number of computation operations and the number of memory operations; and an expression to set at runtime the window type to memory bound window if the arithmetic intensity is less than a threshold and otherwise to set the window type to computation bound window. 6. The method of claim 1 , wherein the window type of the first window is selected from a group consisting of a computation bound window and a memory bound window. 7. The method of claim 1 , wherein the at least one component of the data processor is selected from a group consisting of: a central processing unit (CPU), a memory bank, a cache memory module, a memory bus, a memory controller, and an application specific accelerator. 8. The method of claim 1 , wherein the at least one parameter of the data processor is selected from a group consisting of: a transition latency associated with transitioning operation of at least one component of the data processor from a first frequency to a second frequency different from the first frequency; time to execute a compute operation; time to execute a memory operation; static power consumed by at least one component of the data processor; dynamic power consumed by at least one component of the data processor during a compute operation; and dynamic power consumed by at least one component of the data processor during a memory operation. 9. The method of claim 1 , wherein the at least one characteristic of the first window is selected from a group consisting of: a count of compute operations, a count of memory operations, an estimated compute time, an estimated number of compute cycles, an estimated number of data access cycles; and a memory footprint. 10. The method of claim 1 , wherein the parameter related to compute operations is selected from a group consisting of: a count of compute operations, an estimated number of cycles associated with the compute operations, a measured number of cycles associated with the compute operations, an estimated time required for the compute operations, a measured time required for the compute operations, an estimated energy required by the compute operations, a measured energy required by the compute operations, an estimated power required by the compute operations, and a measured power required by the compute operations. 11. The method of claim 1 , wherein: the power control operation further changes an operating frequency of a memory bus of the data processor from a second memory bus frequency to a first memory bus frequency that is less than the second memory bus frequency. 12. The method of claim 1 , wherein the parameter related to memory operations is selected from a group consisting of: a count of memory operations, an estimated number of cycles associated with the memory operations, a measured number of cycles associated with the memory operations, an estimated time required for the memory operations, a measured time required for the memory operations, an estimated energy required by the memory operations, a measured energy required by the memory operations, an estimated power required by the memory operations, and a measured power required by the memory operations. 13. The method of claim 1 , wherein: the power control operation further changes an operating frequency of a memory bus of the data processor from a first memory bus frequency to a second memory bus frequency that is greater than the first memory bus frequency. 14. The method of claim 1 , wherein: the power control operation is based on, at least in part, an operation count associated with the first window, the operation count being determined at runtime; and the power control operation modifies at runtime at least one attribute of at least one component of the data processor only if the operation count is greater than a threshold. 15. The method of claim 1 , further comprising performing by the compilation processor the steps of: generating within the program a second window; determining window type of the second window; inserting a power control operation in the second window based on, at least in part, at least one of: at least one parameter of the data processor, at least one cha

Assignees

Inventors

Classifications

  • Cross-Sectional Technologies · mapped topic

  • G06F8/4432Primary

    Reducing the energy consumption · CPC title

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10180828B2 cover?
A compilation system generates one or more energy windows in a program to be executed on a data processors such that power/energy consumption of the data processor can be adjusted in which window, so as to minimize the overall power/energy consumption of the data processor during the execution of the program. The size(s) of the energy window(s) and/or power option(s) in each window can be deter…
Who is the assignee on this patent?
Reservoir Labs Inc, Significs And Elements Llc
What technology area does this patent fall under?
Primary CPC classification G06F8/4432. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 15 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).