Method and apparatus for conducting automated integrated circuit analysis

Patent metadata

Field	Value
Publication number	US-10180402-B2
Application number	US-201314066111-A
Country	US
Kind code	B2
Filing date	Oct 29, 2013
Priority date	Dec 14, 2012
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

A method and apparatus for scanning an integrated circuit comprising a plurality of time-synchronized laser microscopes, each of which is configured to scan the same field of view of an integrated circuit under test that generates a plurality of images of the integrated circuit under test, a data processor, coupled to the laser scanning microscope, for processing the plurality of images, comprising, a netlist extractor (NE) that produces one or more netlists defining structure of the integrated circuit under test.

First claim

The invention claimed is:

1. An apparatus for scanning an integrated circuit comprising:
a plurality of laser scanning microscopes comprising different wavelengths of laser light and configurable to operate using different scanning patterns and laser modulation frequencies, configured to pump a same field of view of at least a portion of the integrated circuit with photocarriers having at least one different wavelength, scanning pattern or modulation frequency to cause changes in electrical characteristics of at least the portion of the integrated circuit and generate a plurality of multi-dimensional images of the electrical characteristics of the integrated circuit; and
a data processor, coupled to the laser scanning microscope, for processing the plurality of multi-dimensional images, the data processor comprising:
a netlist extractor (NE) that, using the plurality of multi-dimensional images, produces one or more netlists defining structures of the integrated circuit.

2. The apparatus of claim 1 wherein the plurality of images form a hyper-dimensional representation of the integrated circuit under test.

3. The apparatus of claim 1 wherein the NE uses multimodal processing of the plurality of images and defines unique features based on the plurality of images.

4. The apparatus of claim 1 wherein the data processor simultaneously interacts with a database, distributed computing cluster and the plurality of microscopes and the database comprises library information, data and analysis results.

5. The apparatus of claim 1 wherein the laser scanning microscope utilizes a pump/probe technique to generate the plurality of images.

6. The apparatus of claim 5 wherein the pump/probe technique uses a wavefront distortion mechanism to create a structured pump laser for injecting charge carries into the integrated circuit under test in a predetermined pattern to generate a plurality of charge flow images.

7. The apparatus of claim 6 , further comprising:
a phase-resolving detector for collecting a charge flow signal, wherein a unique color is assigned to each phase of the signal and each phase is plotted as a phase image.

8. The apparatus of claim 6 , wherein a super-resolved image of the integrated circuit under test is constructed using the plurality of charge flow images.

9. The apparatus of claim 1 , wherein the plurality of laser scanning microscopes comprise a pump laser to inject carriers into portions of the integrated circuit under test to suppress activity and a probe laser for detecting the pump laser at other connected transistors in the integrated circuit under test.

10. The apparatus of claim 9 , wherein pump and probe lasers are sub-picosecond, ultrafast lasers.

11. The apparatus of claim 9 , wherein a delay between the pump and probe lasers is adjusted for creating different images based on the delay.

12. The apparatus of claim 9 , wherein the pump laser is further used to suppress an output of a logic cell in the integrated circuit under test, and the probe laser is used to observe an effect of the suppression elsewhere in the integrated circuit under test.

13. The apparatus of claim 1 wherein plurality of images may be generated by at least two of AC or DC reflectivity scans, AC or DC absorption scans, LIVA scans, OBIC scans, single point scans while varying test vectors, charge flow images, ultrafast charge flow images, time-delayed ultrafast charge flow images, activity images, waveform images, or phase images scans at a plurality of laser wavelengths.

14. The apparatus of claim 1 further comprising an AC-coupled RF detector, coupled to the data processor, for measuring RF components of reflectivity signals in a probe laser of the plurality of laser scanning microscopes, in selected frequency ranges.

15. The apparatus of claim 14 wherein the data processor determines a presence and strength of activity at a portion of the integrated circuit under test using correlations between a set of RF reflectivity measurements and statistical mean of a set of waveforms, and the data processor generates an activity map based on the determined presence and strength of activity.

16. The apparatus of claim 15 wherein the activity map is used to determine interconnections between elements of the integrated circuit under test.

17. The apparatus of claim 16 , wherein the activity map is stored in a database and is used for determining where to collect RF waveform data from the integrated circuit under test, the RF waveform data is collected and stored in the database, and unique waveforms are identified and used to identify electrical connections between regions of the integrated circuit under test.

18. A method for scanning an integrated circuit comprising:
using a plurality of laser scanning microscopes, pumping a same field of view of the integrated circuit with photocarriers having at least one different wavelength, scanning pattern or modulation frequency to cause changes in electrical characteristics of at least a portion of the integrated circuit and generate a plurality of multi-dimensional images of the electrical characteristics of the integrated circuit; and
processing the plurality of multi-dimensional images to produce a netlist defining a structure of the integrated circuit.

19. The method of claim 18 wherein the plurality of images form a hyper-dimensional representation of the integrated circuit under test.

20. The method of claim 18 wherein multimodal processing of the plurality of images is used to create hyper-dimensional descriptors for regions of the integrated circuit under test.

21. The method of claim 20 further comprising:
detecting objects from a library of objects using the multimodal processing;
selecting one or more areas of the integrated circuit under test to measure activity; and
collecting waveform data from the one or more areas with activity.

22. The method of claim 21 , further comprising:
constructing additional dimensions for the multimodal processing using the collected waveform data and their corresponding areas;
correlating waveform data using a distributed computing cluster; and
identifying unique nodes in the integrated circuit under test, the unique nodes indicating electrically connected portions of the integrated circuit under test.

23. The method of claim 22 , further comprising:
associating the unique nodes with the collected waveform data through a statistical average of all waveforms with correlations above a predetermined threshold amount.

24. The method of claim 23 , further comprising:
identifying node assignments of new waveforms and their associated coordinates on the integrated circuit under test using the correlation waveform data and statistically averaged waveforms.

25. The method of claim 24 , further comprising:
constructing a netlist, using the unique nodes, their locations and library objects, in a format of at least one of SPICE or Verilog.

Assignees

• Stanford Res Inst Int

Inventors

• Stoker David S
• Matlin Erik Frank
• Agrawal Motilal
• Potthast James R
• Troy Neil William

Classifications

• G01R31/311

  of integrated circuits {(G01R31/31728 takes precedence)} · CPC title

• G01N21/95 Primary

  characterised by the material or shape of the object to be examined (G01N21/89 - G01N21/91, G01N21/94 take precedence) · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5081

  Physics · mapped topic