Capacitor structure with acoustic noise self-canceling characteristics

Patent metadata

Field	Value
Publication number	US-10179254-B2
Application number	US-201615086813-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Sep 21, 2015
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

This application relates to capacitors that resist deformation because of the configuration of their conductive and dielectric layers. The capacitors are multilayer capacitors that include multiple dielectric and conductive layers. The dielectric layers can be arranged in a way that creates a rigid barrier or dead zone, which can resist mechanical deformation when the multilayer capacitor is charged. In some embodiments, two or more multilayer capacitors are stacked together in an arrangement that causes each of the multilayer capacitors to cancel any deformations of the other when the multilayer capacitors are charged. In this way, noise exhibited by the multilayer capacitors can be reduced.

First claim

What is claimed is:

1. A multilayer capacitor, comprising:
a first plurality of conductive layers, each conductive layer of the first plurality of conductive layers defining a respective first electrode and a respective second electrode, wherein each respective first electrode and each respective second electrode are connected to a first terminal of the multilayer capacitor and wherein each respective first electrode is spaced apart from each respective second electrode;
a second plurality of conductive layers, each conductive layer of the second plurality of conductive layers defining a respective third electrode and a respective fourth electrode, wherein each respective third electrode and each respective fourth electrode are connected to a second terminal of the multilayer capacitor and wherein each respective third electrode is spaced apart from each respective fourth electrode; and
a plurality of dielectric layers, each respective dielectric layer disposed between a first respective conductive layer from the first plurality of conductive layers and a second respective conductive layer from the second plurality of conductive layers, wherein a portion of each respective dielectric layer is disposed between the first and the second electrodes of the respective first conductive layer and between the third and the fourth electrodes of the respective second conductive layer such that the plurality of dielectric layers form a dielectric barrier that extends through the first and second plurality of conductive layers and from a top of the multilayer capacitor to a bottom of the multilayer capacitor and between each of the first and the second electrodes and each of the third and the fourth electrodes to resist deformation of the multilayer capacitor caused by the multilayer capacitor receiving a charge.

2. The multilayer capacitor of claim 1 , wherein each conductive layer of the first plurality of conductive layers and the second plurality of conductive layers is monolithically bonded to a corresponding adjacent dielectric layers.

3. The multilayer capacitor of claim 1 , wherein the dielectric barrier is cross shaped.

4. The multilayer capacitor of claim 1 , wherein each dielectric layer of the plurality of dielectric layers comprises barium or titanium.

5. The multilayer capacitor of claim 1 , wherein the dielectric barrier comprises a wall that bisects the multilayer capacitor.

6. The multilayer capacitor of claim 1 , wherein a cross section of the dielectric barrier is defined by an inner edge of at least one conductive layer of the first or second plurality of conductive layers.

7. A method to produce a multilayer capacitor, comprising:
printing a respective first conductive electrode onto each dielectric layer of a first plurality of dielectric layers, wherein each first conductive electrode is configured to couple a first terminal of the multilayer capacitor;
printing a respective second conductive electrode onto each dielectric layer of the first plurality of dielectric layers, wherein each respective second conductive electrode is separated from each respective first conductive electrode, and wherein each second conductive electrode is configured to couple to the first terminal;
printing a respective third conductive electrode onto each dielectric layer of a second plurality of dielectric layers, wherein each third conductive electrode is configured to couple a second terminal of the multilayer capacitor;
printing a fourth respective conductive electrode onto each dielectric layer of the second plurality of dielectric layers, wherein the fourth conductive electrode is separated from the third conductive electrode, and wherein each fourth conductive electrode is configured to couple to the second terminal; and
stacking the first plurality of dielectric layers and the second plurality of dielectric layers to form the multilayer capacitor, wherein the multilayer capacitor comprises a dielectric barrier that extends from a top to a bottom of the multilayer capacitor and between each respective first and second conductive electrodes and each respective third and fourth conductive electrodes, and wherein the dielectric barrier is configured to resist deformation of the multilayer capacitor caused by the multilayer capacitor receiving a charge.

8. The method of claim 7 , wherein the dielectric barrier comprises a cross-shaped barrier, a circular barrier, an oval barrier, or a double cross-shaped barrier.

9. The method of claim 7 , wherein the dielectric barrier comprises a wall that bisects the multilayer capacitor.

10. The method of claim 7 , comprising coating a first edge of the multilayer capacitor to form the first terminal and coating a second edge of the multilayer capacitor to form the second terminal.

11. A multilayer ceramic capacitor, comprising:
a first plurality of ceramic layers, each of the first plurality of ceramic layers having a first conductive portion and a second conductive portion, the first conductive portion being separated from the second conductive portion by a first intermediate ceramic portion of the ceramic layer, and each of the first and second conductive portions having a respective first and second terminal portions; and
a second plurality of ceramic layers, each of the second plurality of ceramic layers having a third conductive portion and a fourth conductive portion, the third conductive portion being separated from the fourth conductive portion by a second intermediate ceramic portion of the ceramic layer, and each of the third and fourth conductive portions having a respective first and second terminal portions; and
wherein each of the first plurality of ceramic layers is interposed between respective ceramic layers of the second plurality of ceramic layers such that each first intermediate ceramic portions of the first plurality of ceramic layers and each second intermediate ceramic portion of the second plurality of ceramic layers are aligned to form a dielectric barrier that extends from a top to a bottom of the multilayer ceramic capacitor between the respective first and second conductive portions of the first plurality of ceramic layers and between the respective third and fourth conductive portions of the second plurality of ceramic layers, wherein the first and second terminal portions of the first plurality of ceramic layers extend in a first direction, and wherein the first and second terminal portions of the second plurality of ceramic layers extend in a second direction different from the first direction.

12. The multilayer ceramic capacitor of claim 11 , wherein the first conductive portions and the third conductive portions comprise a first capacitor of the multilayer ceramic capacitor, and wherein the second conductive portions and the fourth conductive portions comprise a second ceramic capacitor of the multilayer ceramic capacitor.

13. The multilayer ceramic capacitor of claim 11 , wherein the dielectric barrier comprises a cross-shape, a circular shape, an oval shape, or a double-cross shape.

14. The multilayer ceramic capacitor of claim 11 , wherein the ceramic layers of the first and second plurality of ceramic layers comprise barium, or titanium, or any combination thereof.

15. The multilayer ceramic capacitor of claim 11 , comprising a first terminal configured to electrically couple to the first and second terminal portions of the first plurality of ceramic layers, and a second terminal configured to electrically couple to the first and second terminal portions of the second plurality of ceramic layers.

Assignees

• Apple Inc

Inventors

• Martinez Paul A
• Sauers Jason C
• Arnold Shawn X

Classifications

• A62C31/22 Primary

  specially adapted for piercing walls, heaped materials, or the like · CPC title

• H01G4/012

  Form of non-self-supporting electrodes · CPC title

• H01G4/38

  Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

• A62C33/04

  Supports or clamps for fire hoses · CPC title

• H01G4/1218

  based on titanium oxides or titanates (H01G4/1245 takes precedence) · CPC title