Technologies for aggregation-based message synchronization

Patent metadata

Field	Value
Publication number	US-10178041-B2
Application number	US-201514862854-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Sep 23, 2015
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

Technologies for aggregation-based message processing include multiple computing nodes in communication over a network. A computing node receives a message from a remote computing node, increments an event counter in response to receiving the message, determines whether an event trigger is satisfied in response to incrementing the counter, and writes a completion event to an event queue if the event trigger is satisfied. An application of the computing node monitors the event queue for the completion event. The application may be executed by a processor core of the computing node, and the other operations may be performed by a host fabric interface of the computing node. The computing node may be a target node and count one-sided messages received from an initiator node, or the computing node may be an initiator node and count acknowledgement messages received from a target node. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. A computing node for aggregate message processing, the computing node comprising:
messaging circuitry to (i) receive a message from a remote computing node in a message buffer, (ii) increment, by a network interface controller of the computing node, an event counter of the computing node based on a size of the message in response to receipt of the message, (iii) determine, by the network interface controller, whether an event trigger is satisfied in response to an increment of the event counter, wherein to determine whether the event trigger is satisfied comprises to determine whether the event counter has a predefined relationship to a size of the message buffer, (iv), and write, by the network interface controller, a completion event to an event queue in response to a determination that the event trigger is satisfied, wherein the event queue is included in a memory of the computing node, and wherein the event queue is located at a first cache line of the memory and the event counter is located at a second cache line of the memory other than the first cache line, and wherein the memory is separate from the network interface controller; and
application circuitry to monitor, by an application executed by a processor core of the computing node, the event queue in the memory for the completion event, wherein to monitor the event queue in the memory comprises to access the memory by the processor core via a coherent cache.

2. The computing node of claim 1 , further comprising:
a host fabric interface, wherein the host fabric interface comprises the network interface controller; and
a processor, wherein the processor comprises the processor core and the host fabric interface.

3. The computing node of claim 2 , wherein to write the completion event to the event queue comprises to process, by the host fabric interface, a triggered put message to the computing node.

4. The computing node of claim 1 , wherein to monitor the event queue comprises to poll the event queue in the memory.

5. The computing node of claim 1 , wherein the application circuitry is further to:
determine, by the application, whether the completion event has been written to the event queue in response to a monitoring of the event queue; and
process, by the application, a message buffer in response to a determination that the completion event has been written to the event queue, wherein the message buffer is included in the memory of the computing node.

6. The computing node of claim 1 , wherein:
the computing node comprises an initiator computing node;
the remote computing node comprises a target computing node;
the application circuitry is further to write, by the application, an initiator message in a message buffer, wherein the message buffer is included in the memory of the computing node;
the messaging circuitry is further to transmit the initiator message from the message buffer to the remote computing node;
to receive the message from the remote computing node comprises to receive an acknowledgement message from the remote computing node in response to transmission of the initiator message; and
to increment the event counter comprises to increment the event counter in response to receipt of the acknowledgement message.

7. The computing node of claim 6 , wherein:
the application circuitry is further to write, by the application, a plurality of initiator messages in the message buffer, wherein the plurality of initiator messages includes the initiator message; and
to determine whether the event trigger is satisfied comprises to compare the event counter to a count of the plurality of initiator messages.

8. The computing node of claim 1 , wherein:
the computing node comprises a target computing node;
the remote computing node comprises an initiator computing node;
to receive the message from the remote computing node comprises to receive an initiator message in the message buffer of the computing node, wherein the message buffer is included in the memory of the computing node; and
to increment the event counter comprises to increment the event counter in response to receipt of the initiator message.

9. The computing node of claim 1 , further comprising:
a host fabric interface, wherein the host fabric interface comprises the messaging circuitry;
wherein to determine whether the event trigger is satisfied comprises to determine whether the message buffer is full.

10. A method for aggregate message processing, the method comprising:
receiving, by a computing node, a message from a remote computing node in a message buffer;
incrementing, by a network interface controller of the computing node, an event counter of the computing node based on a size of the message in response to receiving the message;
determining, by the network interface controller of the computing node, whether an event trigger is satisfied in response to incrementing the event counter, wherein determining whether the event trigger is satisfied comprises determining whether the event counter has a predefined relationship to a size of the message buffer;
writing, by the network interface controller of the computing node, a completion event to an event queue in response to determining that the event trigger is satisfied, wherein the event queue is included in a memory of the computing node, and wherein the event queue is located at a first cache line of the memory and the event counter is located at a second cache line of the memory other than the first cache line, and wherein the memory is separate from the network interface controller; and
monitoring, by an application executed by a processor core of the computing node, the event queue in the memory for the completion event, wherein monitoring the event queue in the memory comprises accessing the memory by the processor core via a coherent cache.

11. The method of claim 10 , wherein monitoring the event queue comprises polling the event queue in the memory.

12. The method of claim 10 , further comprising:
determining, by the application of the computing node, whether the completion event has been written to the event queue in response to monitoring the event queue; and
processing, by the application of the computing node, a message buffer in response to determining the completion event has been written to the event queue, wherein the message buffer is included in the memory of the computing node.

13. The method of claim 10 , wherein the computing node comprises an initiator computing node and the remote computing node comprises a target computing node, the method further comprising:
writing, by the application of the computing node, an initiator message in a message buffer, wherein the message buffer is included in the memory of the computing node; and
transmitting, by the computing node, the initiator message from the message buffer to the remote computing node;
wherein receiving the message from the remote computing node comprises receiving an acknowledgement message from the remote computing node in response to transmitting the initiator message; and
wherein incrementing the event counter comprises incrementing the event counter in response to receiving the acknowledgement message.

14. The method of claim 13 , further comprising:
writing, by the application of the computing node, a plurality of initiator messages in the message buffer, wherein the plurality of initiator messages includes the initiator message;
wherein determining whether the event trigger is satisfied comprises comparing the event counter to a count of the plurality of initiator messages.

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Assignees

• Intel Corp

Inventors

• Dinan James
• Flajslik Mario
• Keppel David
• Hanebutte Ulf R

Classifications

• H04L47/30

  in combination with information about buffer occupancy at either end or at transit nodes · CPC title

• H04L47/10

  Flow control; Congestion control · CPC title

• Y02D50/30

  Cross-Sectional Technologies · mapped topic

• H04L43/16

  Threshold monitoring · CPC title

• H04L43/04

  Processing captured monitoring data, e.g. for logfile generation · CPC title