Digital time converter systems and methods

Patent metadata

Field	Value
Publication number	US-10177774-B2
Application number	US-201715583063-A
Country	US
Kind code	B2
Filing date	May 1, 2017
Priority date	Jun 30, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

First claim

What is claimed is:

1. A digital to time converter (DTC) comprising:
a divider coarse delay component configured to generate a plurality of divider signals from an oscillator signal based on a divider input signal;
a thermometric array configured to generate a medium approximation signal from the plurality of divider signals;
a switched capacitor array configured to generate a delay signal from the medium approximation signal; and
a first circuit configured to combine a first correction with higher order bits of a converter input signal to generate the divider input signal, wherein the converter input signal includes lower order bits, middle bits, and higher order bits and the first correction is based on the middle bits of the input signal.

2. The converter of claim 1 , further comprising a lookup table configured to generate the first correction, wherein the lookup table includes a first table configured to generate the first correction based on the middle bits of the converter input signal.

3. The converter of claim 2 , wherein the lookup table further includes a second table configured to generate an inverse binary delay correction based on the middle bits of the converter input signal and the switched capacitor array is configured to utilize the inverse binary delay correction.

4. The converter of claim 3 , wherein the lookup table further includes a third table configured to generate a residue correction based on the middle bits of the converter input signal and the switched capacitor array is further configured to utilize the residue correction to generate the delay signal.

5. The converter of claim 1 , wherein the coarse delay component is a multi-modulus divider (MMD).

6. The converter of claim 1 , wherein the middle bits exclude a most significant bit and a least significant bit of the converter input signal.

7. The converter of claim 1 , wherein the switched capacitor array includes a plurality of capacitors connected to an output of the array, wherein the plurality of capacitors are relatively small.

8. The converter of claim 7 , wherein the switch capacitor array includes a plurality of switches each configured to selectively activate an associated capacitor of the array.

9. The converter of claim 8 , further comprising a switched capacitor decoder configured to receive a fine delay signal and generate a plurality of capacitor control signals coupled to the plurality of switches.

10. The converter of claim 1 , wherein the switched capacitor array has substantially linear capacitor steps.

11. The converter of claim 1 , wherein the thermometric array includes a plurality of thermometric inverters.

12. A digital to time converter (DTC) arrangement comprising:
a first circuit configured to combine a residue correction with a first signal to generate a fine delay signal;
a switched capacitor array configured to generate a delay based on a medium approximation signal and the fine delay signal;
wherein the first signal is based on lower order bits of a converter input signal and the residue correction is based on middle bits of the input signal; and
a second circuit configured to generate the first signal based on the lower bits of the converter input signal and an inverse binary delay correction, wherein the residue correction is based on middle bits of the converter input signal and the inverse binary delay correction is based on middle bits of the converter input signal.

13. The arrangement of claim 12 , further comprising a decoder configured to decode the fine delay signal into a plurality of control signals for the switched capacitor array.

14. The arrangement of claim 13 , wherein each capacitor of the switched capacitor array has an associated switch configured to receive one of the plurality of control signals from the decoder.

15. The arrangement of claim 12 , wherein the delay comprises a digital delay that has a substantially finer quantization than the medium approximation signal.

16. The arrangement of claim 12 , further comprising a lookup table comprising:
a first table configured to generate the residue correction based on middle bits of the converter input signal, and
a second table configured to generate the inverse binary delay correction based on the middle bits of the converter input signal.

17. A method of operating a digital time controller (DTC), the method comprising:
generating a thermometric correction based on thermometric bits of a converter input signal;
generating a divider input signal based on the thermometric correction and higher order bits of the converter input signal;
dividing an oscillator signal by a divider based on the divider input signal to generate a plurality of divider signals;
generating a medium approximation signal from the plurality of divider signals based on the thermometric correction; and
generating a delay from the medium approximation signal based on a residue correction using an array of switched capacitors.

18. The method of claim 17 , wherein the divider is a multi modulus divider (MMD) and is used to generate the plurality of divider signals.

19. The method of claim 17 , wherein generating the delay is further based on an inverse binary delay correction, wherein the inverse binary delay correction is provided from a look up table based on the thermometric bits.

20. The DTC arrangement of claim 12 , further comprising a thermometric array configured to generate the medium approximation signal from a coarse approximation and a thermometric correction.

21. The DTC arrangement of claim 20 , further comprising a divider configured to generate the coarse approximation based on an oscillator signal.

Assignees

• Intel Ip Corp

Inventors

• Palaskas Georgios Yorgos
• Madoglio Paolo
• Preyler Peter
• Banin Rotem

Classifications

• H03M1/466

  using switched capacitors · CPC title

• H03M5/02

  Conversion to or from representation by pulses · CPC title

• H03M1/68

  with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits · CPC title

• H03F3/24

  of transmitter output stages · CPC title

• H03M1/82

  with intermediate conversion to time interval · CPC title