Fractional-N phase locked loop delta sigma modulator noise reduction using charge pump interpolation

Patent metadata

Field	Value
Publication number	US-10177772-B2
Application number	US-201615272307-A
Country	US
Kind code	B2
Filing date	Sep 21, 2016
Priority date	Jul 15, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.

First claim

What is claimed is:

1. A phase locked loop, comprising:
a frequency divider included in a feedback path, the frequency divider configured to generate a first frequency divider output and a delayed frequency divider output that is a delayed version of the first frequency divider output;
a charge pump to generate an output current based at least in part on the first frequency divider output and the delayed frequency divider output of the frequency divider; and
at least one phase frequency detector (PFD) coupled between the frequency divider and the charge pump, the at least one PFD generating multiple down control signals;
wherein the charge pump comprises multiple current sources, each of the multiple current sources being controlled based on a corresponding one of the down control signals to generate the output current, the output current comprising a phase interpolation based on the multiple current sources.

2. The phase locked loop of claim 1 , further comprising a voltage controlled oscillator (VCO), in which the delayed frequency divider output is based at least in part on a cycle of the VCO.

3. The phase locked loop of claim 1 , further comprising a delay block that generates the delayed frequency divider output.

4. The phase locked loop of claim 3 , in which the frequency divider includes the delay block.

5. The phase locked loop of claim 1 , in which the at least one PFD receives the first frequency divider output and the delayed frequency divider output as inputs.

6. The phase locked loop of claim 1 , in which the at least one PFD outputs a control signal used by the charge pump to generate the output current.

7. The phase locked loop of claim 1 , further comprising multiple phase frequency detectors, each of the phase frequency detectors further providing an up control signal and a down control signal to drive the charge pump to generate the output current.

8. The phase locked loop of claim 1 , in which the charge pump generates the output current based on a mixture of the first frequency divider output from the frequency divider and the delayed frequency divider output.

9. A method of reducing noise in a phase locked loop comprising:
generating, by a frequency divider included in a feedback path, a first frequency divider output and a delayed frequency divider output that is a delayed version of the first frequency divider output;
generating, by a charge pump, an output current based at least in part on the first frequency divider output and the delayed frequency divider output of the frequency divider;
generating multiple control signals based at least in part on the first frequency divider output and the delayed frequency divider output, the multiple control signals used to generate the output current, the multiple control signals comprising at least two down control signals; and
applying the first frequency divider output to an up control of the charge pump and the delayed frequency divider output to a down control of the charge pump.

10. The method of claim 9 , in which the generated output current is based on a mixture of the first frequency divider output from the frequency divider and the delayed frequency divider output.

11. The method of claim 9 , further comprising generating the output current based at least in part on a weighting function for a charge pump current.

12. The method of claim 9 , further comprising:
receiving, via at least one phase frequency detector, the first frequency divider output and the delayed frequency divider output as inputs.

13. The method of claim 9 , in which each of the at least two down control signals is used to control a current source of multiple current sources of the charge pump such that the output current represents a phase interpolation based on the multiple current sources.

14. A phase locked loop comprising:
means for generating a first frequency divider output and a delayed frequency divider output that is a delayed version of the first frequency divider output;
means for generating an output current based at least in part on the first frequency divider output and the delayed frequency divider output;
means for generating multiple control signals based at least in part on the first frequency divider output and the delayed frequency divider output, the multiple control signals used to generate the output current, the multiple control signals comprising at least two down control signals; and
means for applying the first frequency divider output to an up control of the means for generating the output current and the delayed frequency divider output to a down control of the means for generating the output current.

15. The phase locked loop of claim 14 , further comprising means for controlling one or more current sources to produce an up control of the means for generating the output current or a down control of the means for generating the output current.

16. The phase locked loop of claim 14 , in which the output current is generated based at least in part on a weighting function for a current of the means for generating the output current.

17. The phase locked loop of claim 14 , further comprising means for generating the delayed frequency divider output.

18. The phase locked loop of claim 14 , further comprising at least one phase frequency detector coupled between the means for generating the first frequency divider output and the means for generating the output current.

19. The phase locked loop of claim 14 , further comprising a first means for generating a first current and a second means for generating a second current, the first means for generating the first current and the second means for generating the second current being controlled according to a corresponding one of the multiple control signals such that the output current represents a phase interpolation based on the first current and the second current.

Assignees

• Qualcomm Inc

Inventors

• Zhuang Jingcheng
• Chen Xinhua
• Bossu Frederic
• Tang Yiwu

Classifications

• H03L7/1974

  for fractional frequency division · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title