Nulling reverse recovery charge in DC/DC power converters

Patent metadata

Field	Value
Publication number	US-10177659-B2
Application number	US-201615356894-A
Country	US
Kind code	B2
Filing date	Nov 21, 2016
Priority date	Jul 19, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A switching mode power converter circuit and a method are presented. The circuit comprises a first transistor switch and a second transistor switch coupled in series between an input voltage level and ground. There is a control circuit for controlling switching operation of the first transistor switch and the second transistor switch. There is a detection circuit for sensing a voltage at an intermediate node arranged between the first transistor switch and the second transistor switch, for deriving an indication of a slope of the sensed voltage, and for generating a switching control signal for the control circuit on the basis of the derived indication of the slope of the sensed voltage. The control circuit sets a first timing for activating the first transistor switch and/or a second timing for activating the second transistor switch on the basis of the switching control signal.

First claim

What is claimed is:

1. A switching mode power converter circuit, comprising:
a first transistor switch and a second transistor switch coupled in series between an input voltage level and ground;
a control circuit for controlling switching operation of the first transistor switch and the second transistor switch; and
a detection circuit for sensing a voltage at an intermediate node arranged between the first transistor switch and the second transistor switch, for deriving an indication of a slope of the sensed voltage, and for generating a switching control signal for the control circuit on the basis of the derived indication of the slope of the sensed voltage,
wherein the control circuit is configured to set a first timing for activating the first transistor switch and/or a second timing for activating the second transistor switch on the basis of the switching control signal;
the detection circuit comprises a slope detector circuit;
the slope detector circuit is configured to:
derive the indication of the slope of the sensed voltage; and
generate one or more intermediate signals indicative of respective timings at which a magnitude of the slope of the sensed voltage exceeds a predetermined threshold; and

the slope detector circuit comprises:
a current mirror of two gate-connected transistors; and
a comparator,
wherein each transistor of the current mirror is coupled in series with a respective current source;
a first node between one of the transistors and its respective current source is coupled to a second node between the other one of the transistors and its respective current source via a resistance element;
the first node is coupled to the intermediate node arranged between the first and second transistor switches;
the second node is coupled to an input port of the comparator; and
an output of the comparator serves as one of the one or more intermediate signals.

2. The switching mode power converter circuit according to claim 1 , wherein the switching control signal is indicative of a dead time of the switching mode power converter circuit.

3. The switching mode power converter circuit according to claim 1 , wherein the slope detector circuit is configured to:
generate a first intermediate signal indicative of respective timings at which the slope of the sensed voltage exceeds a predetermined positive threshold; and
generate a second intermediate signal indicative of respective timings at which the slope of the sensed voltage drops below a predetermined negative threshold.

4. The switching mode power converter circuit according to claim 1 , wherein the detection circuit is at least partially disabled for at least a portion of the period of time during which either one of the first transistor switch or the second transistor switch is activated.

5. The switching mode power converter circuit according to claim 2 , wherein the control circuit is configured to set the first timing and/or the second timing on the basis of the switching control signal in such a manner that the dead time of the switching mode power converter circuit is reduced.

6. A switching mode power converter circuit, comprising:
a first transistor switch and a second transistor switch coupled in series between an input voltage level and ground;
a control circuit for controlling switching operation of the first transistor switch and the second transistor switch; and
a detection circuit for sensing a voltage at an intermediate node arranged between the first transistor switch and the second transistor switch, for deriving an indication of a slope of the sensed voltage, and for generating a switching control signal for the control circuit on the basis of the derived indication of the slope of the sensed voltage,
wherein the control circuit is configured to set a first timing for activating the first transistor switch and/or a second timing for activating the second transistor switch on the basis of the switching control signal;
the detection circuit comprises a slope detector circuit;
the slope detector circuit is configured to:
derive the indication of the slope of the sensed voltage; and
generate one or more intermediate signals indicative of respective timings at which a magnitude of the slope of the sensed voltage exceeds a predetermined threshold; the detection circuit comprises a time-to-digital conversion circuit; and
the time-to-digital conversion circuit is configured to generate, as the switching control signal, a digital signal indicative of a dead time of the switching mode power converter circuit on the basis of the one or more intermediate signals; and
the time-to-digital conversion circuit comprises:
a delay line comprising a plurality of inverters; and
a shift register,
wherein the shift register is clocked by one of the one or more intermediate signals;
another one of the one or more intermediate signals is fed to the delay line; and
for each inverter among the plurality of inverters, an output of the respective inverter is fed to a respective corresponding stage of the shift register.

7. The switching mode power converter circuit according to claim 6 , wherein the switching control signal is indicative of a dead time of the switching mode power converter circuit.

8. The switching mode power converter circuit according to claim 6 , wherein the slope detector circuit is configured to:
generate a first intermediate signal indicative of respective timings at which the slope of the sensed voltage exceeds a predetermined positive threshold; and
generate a second intermediate signal indicative of respective timings at which the slope of the sensed voltage drops below a predetermined negative threshold.

9. The switching mode power converter circuit according to claim 6 , wherein the detection circuit is at least partially disabled for at least a portion of the period of time during which either one of the first transistor switch or the second transistor switch is activated.

10. The switching mode power converter circuit according to claim 7 , wherein the control circuit is configured to set the first timing and/or the second timing on the basis of the switching control signal in such a manner that the dead time of the switching mode power converter circuit is reduced.

11. A method of operating a switching mode power converter circuit having a first transistor switch and a second transistor switch coupled in series between an input voltage level and ground, the method comprising:
sensing a voltage at an intermediate node arranged between the first transistor switch and the second transistor switch;
deriving an indication of a slope of the sensed voltage;
generating a switching control signal on the basis of the derived indication of the slope of the sensed voltage;
controlling switching operation of the first transistor switch and the second transistor switch in accordance with the switching control signal; and
generating one or more intermediate signals indicative of respective timings at which a magnitude of the slope of the sensed voltage exceeds a predetermined threshold; and
generating, as the switching control signal, a digital signal indicative of a dead time of the switching mode power converter circuit on the basis of the one or more intermediate signals,
wherein said controlling involves setting a first timing for activating the first transistor switch and/or a second timing for activating the second transistor switch on the basis of the switching control signal; and
generating the digital signal involves:
clocking a shift register by one of the one or more intermediate signals;
feeding another one of the one or more intermediate signals to a delay line

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Dalena Francesco
• Nizza Nicolo
• Gerna Danilo
• Pardi Enrico
• Scaldaferri Stefano
• Morello Alexandre
• Baldetti Tommaso

Classifications

• H02M3/1588 Primary

  comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence) · CPC title

• H02M2001/0051

  Electricity · mapped topic

• H02M1/38

  Means for preventing simultaneous conduction of switches · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title