Inrush current limitation circuit and method

US10177554B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10177554-B2
Application numberUS-201615048632-A
CountryUS
Kind codeB2
Filing dateFeb 19, 2016
Priority dateFeb 19, 2016
Publication dateJan 8, 2019
Grant dateJan 8, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method and circuit for a power supply unit (PSU) suitable for use in an information handling system to detect an inrush current reaching an inrush current threshold, to fully turning off, by a control circuit of the PSU, a series transistor to block the inrush current, to transfer, while the series transistor is fully turned off, magnetic energy stored in a boost choke to a bulk capacitor, and to fully turn on, by the control circuit of the PSU, the series transistor again immediately after the series transistor was in a fully turned off state, wherein the fully turning on occurs after the magnetic energy stored in the boost choke has been transferred to the bulk capacitor.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: detecting an inrush current in a power supply unit (PSU) for an information handling system reaching an inrush current threshold; upon detecting the inrush current reaching the inrush current threshold, fully turning off, by a control circuit of the PSU, a series transistor to block the inrush current; while the series transistor is fully turned off, transferring magnetic energy stored in a boost choke to a bulk capacitor; and fully turning on, by the control circuit of the PSU, the series transistor again immediately after the series transistor was in a fully turned off state, wherein the fully turning on occurs after the magnetic energy stored in the boost choke has been transferred to the bulk capacitor. 2. The method of claim 1 , further comprising: controlling a magnetic energy shunt transistor to provide a first conductive path from a first end of the boost choke to a first end of the bulk capacitor via a series combination of a magnetic energy shunt diode and the magnetic energy shunt transistor; and providing a second conductive path from a second end of the boost choke to a second end of the bulk capacitor. 3. The method of claim 2 , wherein the control circuit is further configured to maintain a boost transistor in a non-conducting state and the magnetic energy shunt transistor in a conducting state while a voltage difference between a bridge diode peak voltage and a bulk capacitor voltage is sufficient to result in the inrush current reaching the inrush current threshold. 4. The method of claim 1 , wherein the, while the series transistor is fully turned off, transferring the magnetic energy stored in the boost choke to the bulk capacitor comprises: transferring the magnetic energy stored in the boost choke to the bulk capacitor via a magnetic energy shunt winding of the boost choke electrically insulated from a main winding of the boost choke, wherein a magnetic energy shunt diode and a magnetic energy shunt transistor in series are coupled the magnetic energy shunt winding of the boost choke, wherein the main winding of the boost choke is coupled to a bridge diode, wherein a boost diode is coupled between the main winding of the boost choke and the magnetic energy shunt winding of the boost choke. 5. The method of claim 1 , wherein the control circuit is further configured to maintain a boost transistor in a non-conducting state while a voltage difference between a bridge diode peak voltage and a bulk capacitor voltage is sufficient to result in the inrush current reaching the inrush current threshold. 6. The method of claim 1 , wherein the control circuit is further configured to fully turn off for less than one millisecond the series transistor when the inrush current reaches the inrush current threshold. 7. A circuit comprising: a bridge diode; a boost choke coupled to the bridge diode; a boost transistor coupled to the boost choke; a boost diode coupled to the boost choke and to the boost transistor; a bulk capacitor coupled to the boost diode; a series transistor coupled in series between the bridge diode and the bulk capacitor; and a control circuit coupled to the series transistor, the control circuit configured to fully turn on the series transistor until an inrush current reaches an inrush current threshold and to fully turn off the series transistor when the inrush current reaches the inrush current threshold, wherein magnetic energy stored in the boost choke is transferred to the bulk capacitor while the series transistor is fully turned off, wherein the control circuit is further configured to fully turn on the series transistor again immediately after the series transistor was in a fully turned off state, wherein the fully turning on the series transistor again occurs after the magnetic energy stored in the boost choke has been transferred to the bulk capacitor. 8. The circuit of claim 7 , further comprising: a magnetic energy shunt diode; and a magnetic energy shunt transistor, the magnetic energy shunt diode and the magnetic energy shunt transistor coupled in series with each other and coupled to the boost choke and to the bulk capacitor. 9. The circuit of claim 8 , wherein the control circuit is further configured to maintain the boost transistor in a non-conducting state and the magnetic energy shunt transistor in a conducting state while a voltage difference between a bridge diode peak voltage and a bulk capacitor voltage is sufficient to result in the inrush current reaching the inrush current threshold. 10. The circuit of claim 7 , wherein the magnetic energy shunt diode and the magnetic energy shunt transistor in series are coupled a magnetic energy shunt winding of the boost choke, wherein a main winding of the boost choke is coupled to the bridge diode. 11. The circuit of claim 7 , wherein the boost diode is coupled between the main winding of the boost choke and the magnetic energy shunt winding of the boost choke. 12. The circuit of claim 7 , wherein the control circuit is further configured to maintain the boost transistor in a non-conducting state while a voltage difference between a bridge diode peak voltage and a bulk capacitor voltage is sufficient to result in the inrush current reaching the inrush current threshold. 13. The circuit of claim 7 , wherein the control circuit is further configured to fully turn off for less than one millisecond the series transistor when the inrush current reaches the inrush current threshold. 14. A power supply unit (PSU) comprising: a bridge diode; a boost choke coupled to the bridge diode; a boost transistor coupled to the boost choke; a boost diode coupled to the boost choke and to the boost transistor; a bulk capacitor coupled to the boost diode; a series transistor coupled in series between the bridge diode and the bulk capacitor; and a control circuit coupled to the series transistor, the control circuit configured to fully turn on the series transistor until an inrush current reaches an inrush current threshold and to fully turn off the series transistor when the inrush current reaches the inrush current threshold, wherein magnetic energy stored in the boost choke is transferred to the bulk capacitor while the series transistor is fully turned off, wherein the control circuit is further configured to fully turn on the series transistor again immediately after the series transistor was in a fully turned off state, wherein the fully turning on the series transistor again occurs after the magnetic energy stored in the boost choke has been transferred to the bulk capacitor. 15. The PSU of claim 14 , further comprising: a magnetic energy shunt diode; and a magnetic energy shunt transistor, the magnetic energy shunt diode and the magnetic energy shunt transistor coupled in series with each other and coupled to the boost choke and to the bulk capacitor. 16. The PSU of claim 15 , wherein the control circuit is further configured to maintain the boost transistor in a non-conducting state and the magnetic energy shunt transistor in a conducting state while a voltage difference between a bridge diode peak voltage and a bulk capacitor voltage is sufficient to result in the inrush current reaching the inrush current threshold. 17. The PSU of claim 14 , wherein the magnetic energy shunt diode and the magnetic energy shunt transistor in series are coupled a magnetic energy shunt winding of the boost choke, wherein a main winding of the boost choke is coupled to the bridge diode. 18. The PSU of claim 14 , wherein the boos

Assignees

Inventors

Classifications

  • G06F1/305Primary

    in the event of power-supply fluctuations · CPC title

  • limiting inrush current on switching on of inductive loads subjected to remanence, e.g. transformers · CPC title

  • H02H3/08Primary

    responsive to excess current (responsive to abnormal temperature caused by excess current H02H5/04) · CPC title

  • limiting speed of change of electric quantities, e.g. soft switching on or off (progressive control of electronic switches for eliminating interferences H03K17/16) · CPC title

  • in connection with live-insertion of plug-in units (involving communication with a central processing unit G06F13/40) · CPC title

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What does patent US10177554B2 cover?
A method and circuit for a power supply unit (PSU) suitable for use in an information handling system to detect an inrush current reaching an inrush current threshold, to fully turning off, by a control circuit of the PSU, a series transistor to block the inrush current, to transfer, while the series transistor is fully turned off, magnetic energy stored in a boost choke to a bulk capacitor, an…
Who is the assignee on this patent?
Dell Products Lp
What technology area does this patent fall under?
Primary CPC classification G06F1/305. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 08 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).