Multiple-bits-per-cell voltage-controlled magnetic memory
US-2015137289-A1 · May 21, 2015 · US
US10177303B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10177303-B2 |
| Application number | US-201815877806-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 23, 2018 |
| Priority date | Jan 23, 2017 |
| Publication date | Jan 8, 2019 |
| Grant date | Jan 8, 2019 |
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A magneto-electric magnetic tunnel junction device (ME-MTJ) that permits direct driving of ME-MTJ devices by a prior ME-MTJ device is the unipolar magneto-electric magnetic tunnel junction (UMMTJ) device. The UMMTJ device enables full logic circuitry to be implemented without level shifting between each logic element.
Opening claim text (preview).
The invention claimed is: 1. A unipolar magnetoelectric magnetic tunnel junction device comprising: an electrode; an antiferromagnetic (AFM) substrate; and a level adjusting layer comprising between the electrode and the antiferromagnetic substrate, wherein the level adjusting layer is programmed to offset an input voltage requirement, so the voltage requirement can be switched between states with a positive voltage and a zero voltage. 2. The unipolar magnetoelectric magnetic tunnel junction device of claim 1 , further comprising: a free ferromagnetic (FM) layer; a fixed ferromagnetic (FM) layer; an insulating layer separating the free FM layer and fixed FM layer; and wherein the free FM layer, fixed FM layer, and insulating layer are located between the AFM substrate and the level adjusting layer. 3. The unipolar magnetoelectric magnetic tunnel junction device of claim 2 , further comprising a chromia layer located between the level adjusting layer and the free FM layer. 4. The unipolar magnetoelectric magnetic tunnel junction device of claim 3 , further comprising a gate terminal connected to the electrode, a drain terminal connected to the fixed FM layer, and a source terminal connected to the free FM layer. 5. The unipolar magnetoelectric magnetic tunnel junction device of claim 4 , further comprising a voltage source with voltage applied to the electrode at the gate terminal and free FM layer at the source terminal. 6. The unipolar magnetoelectric magnetic tunnel junction device of claim 1 , wherein the level adjusting layer comprises a floating gate. 7. The unipolar magnetoelectric magnetic tunnel junction device of claim 6 , wherein the floating gate is programmed by applying an appropriate programming voltage through a tunnel junction. 8. The unipolar magnetoelectric magnetic tunnel junction device of claim 1 , wherein the level adjusting layer comprises a ferroelectric layer that can be programmed to a desired state. 9. The unipolar magnetoelectric magnetic tunnel junction device of claim 8 , wherein the programming to the desired state includes applying a voltage to the level adjusting layer sufficient to modify a state of the level adjusting layer. 10. The unipolar magnetoelectric magnetic tunnel junction device of claim 1 , wherein the level adjusting layer comprises an ionic conductor that can be programmed to a desired state. 11. The unipolar magnetoelectric magnetic tunnel junction device of claim 10 , wherein the programming to the desired state includes applying a voltage to the level adjusting layer sufficient to modify a state of the level adjusting layer. 12. A memory device for storing digital data comprising a unipolar magnetoelectric magnetic tunnel junction device comprising: an electrode; an antiferromagnetic (AFM) substrate; and a level adjusting layer comprising between the electrode and the antiferromagnetic substrate, wherein the level adjusting layer is programmed to offset an input voltage requirement, so the voltage requirement can be switched between states with a positive voltage and a zero voltage. 13. The memory device of claim 12 , further comprising: a free ferromagnetic (FM) layer; a fixed ferromagnetic (FM) layer; an insulating layer separating the free FM layer and fixed FM layer; and wherein the free FM layer, fixed FM layer, and insulating layer are located between the AFM substrate and the level adjusting layer. 14. The memory device of claim 13 , further comprising a chromia layer located between the level adjusting layer and the free FM layer. 15. The memory device of claim 14 , further comprising a gate terminal connected to the electrode, a drain terminal connected to the fixed FM layer, and a source terminal connected to the free FM layer. 16. The memory device of claim 15 , further comprising a voltage source with voltage applied to the electrode at the gate terminal and free FM layer at the source terminal. 17. The memory device of claim 12 , wherein the level adjusting layer comprises a floating gate. 18. The memory device of claim 17 , wherein the floating gate is programmed by applying an appropriate programming voltage through a tunnel junction. 19. The memory device of claim 12 , wherein the level adjusting layer comprises a ferroelectric layer that can be programmed to a desired state. 20. The memory device of claim 19 , wherein the programming to the desired state includes applying a voltage to the level adjusting layer sufficient to modify a state of the level adjusting layer.
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