Conductive pad structure for hybrid bonding and methods of forming same

Patent metadata

Field	Value
Publication number	US-10177106-B2
Application number	US-201715800491-A
Country	US
Kind code	B2
Filing date	Nov 1, 2017
Priority date	Dec 18, 2013
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

First claim

What is claimed is:

1. A device comprising:
a first substrate having a pixel array region and a peripheral region surrounding the pixel array region;
a plurality of photodiodes in the pixel array region of the first substrate;
a first redistribution structure over the first substrate;
a first dielectric layer over the first redistribution structure; and
a first conductive pad extending through the first dielectric layer and the first redistribution structure, the first conductive pad being disposed over the peripheral region of the first substrate, a bottommost surface of the first conductive pad being below a bottommost surface of the first redistribution structure, wherein the first conductive pad comprises:
a first portion extending through the first dielectric layer, the first portion having a first width; and
a second portion extending through the first redistribution structure, the second portion having a second width, the second width being different from the first width.

2. The device of claim 1 , wherein the second width is less than the first width.

3. The device of claim 1 , further comprising:
a second substrate;
a second redistribution structure interposed between the second substrate and the first dielectric layer;
a second dielectric layer interposed between the second redistribution structure and the first dielectric layer, the second dielectric layer being in physical contact with first dielectric layer; and
a second conductive pad extending through the second dielectric layer and the second redistribution structure, the second conductive pad being in physical contact with the first conductive pad.

4. The device of claim 3 , wherein a topmost surface of the second conductive pad is above a topmost surface of the second redistribution structure.

5. The device of claim 3 , wherein the second conductive pad comprises:
a third portion extending through the second dielectric layer, the third portion having a third width; and
a fourth portion extending through the second redistribution structure, the fourth portion having a fourth width, the fourth width being different from the third width.

6. The device of claim 5 , wherein the fourth width is less than the third width.

7. The device of claim 1 , further comprising:
a first interconnect structure interposed between the first redistribution structure and the first substrate; and
a second dielectric layer interposed between the first redistribution structure and the first interconnect structure, the second portion of the first conductive pad extending through the second dielectric layer and into the first interconnect structure.

8. A device comprising:
a first substrate having a pixel array region in an interior of the first substrate and a peripheral region at an edge of the first substrate, the peripheral region surrounding the pixel array region;
a plurality of photodiodes in the pixel array region of the first substrate;
a first interconnect structure over the first substrate;
a first dielectric layer over the first interconnect structure; and
a first conductive pad extending through the first dielectric layer and into the first interconnect structure, the first conductive pad being disposed at the edge of the first substrate, a bottommost surface of the first conductive pad being below a topmost surface of the first interconnect structure and above a bottommost surface of the first interconnect structure, wherein the first conductive pad comprises:
a first portion within the first dielectric layer, the first portion having a first width; and
a second portion within the first interconnect structure, the second portion having a second width, the second width being different from the first width.

9. The device of claim 8 , wherein the second width is less than the first width.

10. The device of claim 8 , wherein a difference between the first width and the second width is greater than about 0.05 μm.

11. The device of claim 8 , further comprising:
a first redistribution structure interposed between the first dielectric layer and the first interconnect structure; and
a second dielectric layer interposed between the first redistribution structure and the first interconnect structure, the first conductive pad extending through the second dielectric layer and the first redistribution structure.

12. The device of claim 8 , further comprising:
a second substrate;
logic arrays in the second substrate;
a second interconnect structure interposed between the second substrate and the first dielectric layer;
a second dielectric layer interposed between the second interconnect structure and the first dielectric layer, the second dielectric layer being bonded to the first dielectric layer; and
a second conductive pad extending through the second dielectric layer and into the second interconnect structure.

13. The device of claim 12 , wherein the second conductive pad comprises:
a third portion within the second dielectric layer, the third portion having a third width; and
a fourth portion within the second interconnect structure, the fourth portion having a fourth width, the fourth width being less than the third width.

14. The device of claim 12 , wherein the first conductive pad has a substantially same shape as the second conductive pad.

15. A device comprising:
a first substrate;
a first interconnect structure over the first substrate;
a first redistribution structure over the first interconnect structure;
a first dielectric layer over the first redistribution structure;
a first conductive pad extending through the first dielectric layer and the first redistribution structure, and into the first interconnect structure, the first conductive pad narrowing as the first conductive pad extends through the first redistribution structure toward the first interconnect structure;
a second dielectric layer over the first dielectric layer;
a second redistribution structure over the second dielectric layer;
a second interconnect structure over the second redistribution structure; and
a second conductive pad extending through the second dielectric layer and the second redistribution structure, and into the second interconnect structure.

16. The device of claim 15 , wherein the first conductive pad comprises:
a first portion within the first redistribution structure, the first portion having a first width; and
a second portion within the first interconnect structure, the second portion having a second width, the second width being different from the first width.

17. The device of claim 16 , wherein the second width is less than the first width.

18. The device of claim 15 , wherein the second conductive pad narrows as the second conductive pad extends through the second redistribution structure toward the second interconnect structure.

19. The device of claim 15 , wherein the first dielectric layer is in physical contact with the second dielectric layer, and wherein the first conductive pad is in physical contact with the second conductive pad.

20. The device of claim 15 , wherein the second conductive pad comprises:
a first portion within the second redistribution structure, the first portion having a first width; and
a second portion within the second interconnect structure, the second portion having a second width, the second width being less than the first width.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Sheng-Chau
• Chou Shih Pei
• Chu Yen-Chang
• Chou Cheng-Hsien
• Huang Chih-Hui
• Tu Yeur-Luen

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title