Molded intelligent power module

Patent metadata

Field	Value
Publication number	US-10177080-B2
Application number	US-201715602002-A
Country	US
Kind code	B2
Filing date	May 22, 2017
Priority date	Oct 16, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, an IC, a plurality of leads and a molding encapsulation. The first MOSFET is attached to the first die paddle. The second MOSFET is attached to the second die paddle. The third MOSFET is attached to the third die paddle. The fourth, fifth and sixth MOSFETs are attached to the fourth die paddle. The IC is attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the IC. The IPM is a small-outline package. It reduces system design time and improves reliability. The IC includes boost diodes. It reduces a package size of the IPM.

First claim

The invention claimed is:

1. An intelligent power module (IPM) for driving a motor, the IPM comprising:
a first, second, third and fourth die paddles;
a first transistor attached to the first die paddle;
a second transistor attached to the second die paddle;
a third transistor attached to the third die paddle;
a fourth, fifth, and sixth transistors attached to the fourth die paddle;
an integrated circuit (IC) disposed adjacent to the second and third die paddles; the IC being electrically connected to the first, second, third, fourth, fifth, and sixth transistors;
a plurality of leads; and
a molding encapsulation enclosing the first, second, third, and fourth die paddles, the first, second, third, fourth, fifth, and sixth transistors, and the IC;
wherein the plurality of leads are partially embedded in the molding encapsulation.

2. The IPM of claim 1 further comprising a tie bar having a first end, a second end and a mid-range extension and wherein the mid-range extension of the tie bar is mechanically and electrically connected to a ground lead.

3. The IPM of claim 2 , wherein a first end surface of the first end and a second end surface of the second end of the tie bar are exposed from edge surfaces of the molding encapsulation.

4. The IPM of claim 2 , wherein a power lead is between the ground lead and an isolation lead.

5. The IPM of claim 2 , wherein at least a portion of an upper side edge of the first die paddle, upper side edges of the second and third die paddles, and at least a portion of an upper side edge of the fourth die paddle are co-planar;
wherein a middle section of a lower side edge of the tie bar is parallel to the upper side edges of the second and third die paddles.

6. The IPM of claim 1 , wherein the IC is electrically connected to the first, second, third, fourth, fifth, and sixth transistors by a plurality of gold bonding wires and wherein a plurality of copper bonding wires electrically and mechanically connect the first, second, third, fourth, fifth and sixth transistors to a portion of the plurality of leads.

7. The IPM of claim 1 , wherein a first connecting member connects the first die paddle to a first lead of the plurality of leads;
a second connecting member connects the second die paddle to a second lead of the plurality of leads;
a third connecting member connects the third die paddle to a third lead of the plurality of leads; and
a fourth connecting member connects the fourth die paddle to a fourth lead of the plurality of leads.

8. The IPM of claim 7 , wherein a first isolation lead is between a first low-voltage lead and the first lead;
a second isolation lead is between the first lead and the second lead; and
a third isolation lead is between the second lead and the third lead.

9. The IPM of claim 8 , wherein a fourth isolation lead is between a first selected high-voltage lead and a second selected high-voltage lead.

10. The IPM of claim 9 , wherein the first lead is connected to the second selected high-voltage lead through a printed circuit board and wherein the second lead is connected to the first selected high-voltage lead through the printed circuit board.

11. The IPM of claim 7 , wherein a fifth, sixth and seventh leads of the plurality of leads are directly connected to the fourth connecting member.

12. The IPM of claim 1 , wherein the first transistor is a first metal-oxide-semiconductor field-effect transistor (MOSFET);
the second transistor is a second MOSFET;
the third transistor is a third MOSFET;
the fourth transistor is a fourth MOSFET;
the fifth transistor is a fifth MOSFET; and
the sixth transistor is a sixth MOSFET.

13. The IPM of claim 12 , wherein a first bonding wire connects a source of the first MOSFET to a low-voltage lead;
a second bonding wire connects the source of the first MOSFET to a source of the second MOSFET; and
a third bonding wire connects the source of the second MOSFET to a source of the third MOSFET.

14. The IPM of claim 1 , wherein a first plurality of bonding wires connect the IC to the plurality of leads or connect the IC to the first, second, third, fourth, fifth and sixth transistors; wherein a second plurality of bonding wires connect sources of the first, second, third, fourth, fifth and sixth transistors to a portion of the plurality of leads; wherein the first plurality of bonding wires are gold bonding wires; and wherein the second plurality of bonding wires are copper bonding wires.

15. The IPM of claim 1 further comprising a fifth die paddle, wherein the fourth die paddle is of an inverse letter L shape and wherein the fourth die paddle has a cutout to accommodate a portion of the fifth die paddle to facilitate a compactness of the IPM.

16. The IPM of claim 1 , wherein the fourth die paddle is of an inverse letter L shape; wherein the fourth die paddle has a cutout to accommodate a wire bonding region of the third die paddle; and wherein a bonding wire connects a source of the sixth transistor to the wire bonding region of the third die paddle.

Assignees

• Alpha & Omega Semiconductor Cayman Ltd

Inventors

• Niu Zhiqiang
• Suh Bum-Seok
• Lu Jun
• Cho Wonjin

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/481 Primary

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W20/427

  Power or ground buses · CPC title