Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10176994-B2
Application number	US-201515545732-A
Country	US
Kind code	B2
Filing date	Mar 13, 2015
Priority date	Mar 13, 2015
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A p-type base layer ( 2 ) is formed on a surface of an n-type silicon substrate ( 1 ). First and second n + -type buffer layers ( 8,9 ) 9 are formed on a back surface of the n-type silicon substrate ( 1 ). The first n + -type buffer layer ( 8 ) is formed by a plurality of implantations of protons at different accelerating voltages and has a plurality of peak concentrations with different depths from the back surface of the n-type silicon substrate ( 1 ). The second n + -type buffer layer ( 9 ) is formed by an implantation of a phosphorus. A position of a peak concentration of the phosphorus is shallower from the back surface of the n-type silicon substrate ( 1 ) than positions of peak concentrations of the protons. The peak concentration of the phosphorus is higher than the peak concentrations of the protons. A concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a p-type layer formed on a surface of the semiconductor substrate; and
first and second n-type buffer layers formed on a back surface of the semiconductor substrate,
wherein the first n-type buffer layer is formed by a plurality of implantations of protons at different accelerating voltages and has a plurality of peak concentrations with different depths from the back surface of the semiconductor substrate,
the second n-type buffer layer is formed by an implantation of a phosphorus,
a position of a peak concentration of the phosphorus is shallower from the back surface of the semiconductor substrate than positions of peak concentrations of the protons,
the peak concentration of the phosphorus is higher than the peak concentrations of the protons, and
a concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.

2. The semiconductor device according to claim 1 , wherein the semiconductor device is a diode or an insulated gate bipolar transistor.

3. A method of manufacturing a semiconductor device according to claim 1 , wherein the first n-type buffer layer is formed by performing the plurality of implantations of the protons at different accelerating voltages using an ion implanter for manufacturing semiconductors.

4. The method of manufacturing a semiconductor device according to claim 3 , wherein when performing the plurality of implantations of the protons, the higher the accelerating voltage, the smaller the implantation amount.

5. The method of manufacturing a semiconductor device according to claim 3 , wherein an implantation amount of a profile with a highest accelerating voltage and an implantation amount of a profile with a next highest accelerating voltage among the plurality of implantations of the protons are same.

6. The method of manufacturing a semiconductor device according to claim 3 , wherein an implantation amount of the phosphorus is smaller than an implantation amount of the protons, and
the phosphorus is activated by laser annealing.

7. The method of manufacturing a semiconductor device according to claim 3 , wherein the protons are activated by furnace annealing at 350° C. to 450° C.

8. The method of manufacturing a semiconductor device according to claim 3 , wherein an accelerating voltage of the phosphorus is 1 MeV or lower.

9. The method of manufacturing a semiconductor device according to claim 3 , wherein an accelerating voltage of the protons is 500 keV or higher and 1.5 MeV or lower.

10. The method of manufacturing a semiconductor device according to claim 3 , comprising forming a back electrode on a back surface of the semiconductor substrate; and
performing a heat treatment for obtaining ohmic contact between the back electrode and the semiconductor substrate in a same process as a heat treatment for activating the protons.

11. A semiconductor device comprising:
a semiconductor substrate;
a p-type layer formed on a surface of the semiconductor substrate; and
first and second n-type buffer layers formed on a back surface of the semiconductor substrate,
wherein the first n-type buffer layer comprises protons that have a plurality of peak concentrations with different depths from the back surface of the semiconductor substrate,
the second n-type buffer layer comprises phosphorus,
a position of a peak concentration of the phosphorus is shallower from the back surface of the semiconductor substrate than positions of peak concentrations of the protons,
the peak concentration of the phosphorus is higher than the peak concentrations of the protons, and
a concentration of the protons is higher than a concentration of the phosphorus at the positions of the peak concentrations of the protons.

Assignees

• Mitsubishi Electric Corp

Inventors

• Suzuki Kenji
• Narazaki Atsushi
• Kamibaba Ryu
• Fukada Yusuke
• Nakamura Katsumi

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title