Multilayer ceramic capacitor

Patent metadata

Field	Value
Publication number	US-10176922-B2
Application number	US-201715416892-A
Country	US
Kind code	B2
Filing date	Jan 26, 2017
Priority date	Jan 28, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

In an embodiment, a multilayer ceramic capacitor 10 is constituted in such a way that four capacitive components C1 to C4 that are connected in series are formed between a first internal electrode layer group 14 and a second internal electrode layer group 15 adjacent to it, wherein, among the four capacitive components C1 to C4, the facing area Sc1 that defines the capacitance value of the capacitive component C1 closest to the first external electrode 12 and the facing area Sc4 that defines the capacitance value of the capacitive component C4 closest to the second external electrode 13 are greater than the facing areas Sc2 and Sc3 that define the capacitance values of the two remaining capacitive components C2 and C3, respectively. The multilayer ceramic capacitor is capable of satisfying the needs for both size reduction and voltage resistance increase.

First claim

We claim:

1. A multilayer ceramic capacitor constructed by stacking alternately, with dielectric layers placed in between:
(i) first internal electrode layer groups, each formed on a same plane and comprising:
a first electrode layer connected to a first external electrode;
a second electrode layer connected to a second external electrode; and
n number (n is an integer of 1 or greater) of third electrode layer(s) placed between the first electrode layer and the second electrode layer in a manner not contacting either of them; and

(ii) second internal electrode layer groups, each formed on a same plane and comprising:
n+1 number of fourth electrode layers not connected to either the first external electrode or the second external electrode, being placed in a manner not contacting each other;

wherein m number (m=2(n+1)) of capacitive components are formed between the first internal electrode layer group and the second internal electrode layer group adjacent thereto, each capacitive component capacitively connecting the first internal electrode layer group and the second internal electrode layer group in series via a dielectric layer at an overlapping region where an electrode layer of the first internal electrode layer group and an electrode layer of the second internal electrode layer group face each other;
wherein, among the m number of capacitive components, a facing area of the overlapping region that defines a capacitance value of one capacitive component closest to an end of the first external electrode facing the second external electrode, and a facing area of the overlapping region that defines a capacitance value of one capacitive component closest to an end of the second external electrode facing the first external electrode, are each greater than a facing area of the overlapping region that defines a capacitance value of any one of remaining capacitive components.

2. A multilayer ceramic capacitor according to claim 1 , wherein the facing area of the overlapping region that defines the capacitance value of one capacitive component closest to the first external electrode is equal to the facing area of the overlapping region that defines the capacitance value of one capacitive component closest to the second external electrode.

3. A multilayer ceramic capacitor according to claim 1 , wherein each third electrode layer has a shape which is the same as a shape of each fourth electrode layer as viewed from above.

4. A multilayer ceramic capacitor according to claim 1 , wherein each third electrode layer has a shape which is different from a shape of each fourth electrode layer as viewed from above.

5. A multilayer ceramic capacitor according to claim 1 , wherein n is an integer of 2 or greater, and m is an even number of 6 or greater, and
when the capacitive components are referred to as C( 1 ) to C(m), respectively, from the first external electrode side toward the second external electrode side, and facing areas of the overlapping regions that define capacitance values of C( 1 ) to C(m), respectively, are referred to as Sc( 1 ) to Sc(m), respectively,
a relationship of Sc( 1 ) >Sc( 2 ) >. . . >Sc(m/ 2 ), and a relationship of Sc(m) >. . . >Sc(m/2+2) >Sc(m/2 +1), are satisfied.

6. A multilayer ceramic capacitor according to claim 5 , wherein m is 6 , and Sc( 1 ), Sc( 2 ), and Sc( 3 ) are equivalent to Sc( 6 ), Sc( 5 ), and Sc( 4 ), respectively.

Assignees

• Taiyo Yuden Kk

Inventors

• Inomata Yasuyuki
• Hayashi Shintaro

Classifications

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/01

  Form of self-supporting electrodes · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/242

  the capacitive element surrounding the terminal · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title