Sense amplifier and memory device using the same

Patent metadata

Field	Value
Publication number	US-10176878-B2
Application number	US-201715452885-A
Country	US
Kind code	B2
Filing date	Mar 8, 2017
Priority date	May 2, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.

First claim

What is claimed is:

1. A sense amplifier configured to sense and amplify data of a memory cell, the sense amplifier comprising:
a precharge circuit,
said precharge circuit configured to pre-charge a data line with a power supply voltage,
said precharge circuit configured to pre-charge a reference line with the power supply voltage,
said precharge circuit connected to the data line,
said precharge circuit connected to the reference line,
said data line connected to the memory cell and configured to provide a sensing voltage,
said reference line configured to provide a reference voltage;

a reference voltage generating circuit configured to generate the reference voltage by discharging the reference line based on a reference current, said reference voltage generating circuit configured to adjust an amount of the reference current based on the data of the memory cell; and
a comparator configured to compare the sensing voltage with the reference voltage and is configured to output a comparison result as the data of the memory cell.

2. The sense amplifier of claim 1 , wherein when the sensing voltage is lowered below a critical level, the reference current is decreased, and when the sensing voltage is higher than the critical level, the reference current is increased.

3. The sense amplifier of claim 1 , wherein when the data of the memory cell has a first value, a current amount discharged from the data line is substantially equal to the amount of the reference current when the data of the memory cell has a second value.

4. The sense amplifier of claim 1 , wherein when data of the memory cell has a first value, a voltage down slope of the sensing voltage is substantially equal to the voltage down slope of the reference voltage when the data of the memory cell has a second value.

5. The sense amplifier of claim 1 , wherein the reference voltage generating circuit further comprises:
a discharge circuit configured to generate the reference current and discharge the reference current from the reference line; and
a bias circuit configured to generate a bias voltage that adjusts the amount of the reference current, based on a pseudo sensing voltage output from a pseudo data line, said pseudo data line substantially having an equal voltage level as the data line.

6. The sense amplifier of claim 5 , wherein the current amount discharged from the pseudo data line is substantially equal to the current amount discharged from the data line.

7. The sense amplifier of claim 5 , wherein the bias circuit comprises the pseudo sensing voltage and a non-inverting differential amplifier configured to receive an input voltage at a constant level.

8. The sense amplifier of claim 7 , wherein the bias circuit is configured to generate the bias voltage to increase the reference current when the pseudo sensing voltage is lower than the input voltage, and is configured to generate the bias voltage to decrease the reference current when the pseudo sensing voltage is higher than the input voltage.

9. The sense amplifier of claim 7 , wherein when the data of the memory cell has a first value, an amount of a bias current flowing through the non-inverting differential amplifier is substantially equal to the current amount discharged from the data line.

10. The sense amplifier of claim 7 , wherein the non-inverting differential amplifier includes:
a first transistor receiving the pseudo sensing voltage,
and a second transistor receiving the input voltage,
wherein the reference current is proportional to the current amount flowing through the second transistor.

11. A memory device comprising:
a memory cell array selectively connected to a data line and comprising a plurality of memory cells, wherein each cell is configured to discharge a cell current from the data line according to a stored data during a read operation;
a load transistor which is connected to a pseudo data line and is configured to discharge an equal amount of current as that of the cell current from the pseudo data line; and
a sense amplifier configured to generate a reference voltage based on a pseudo sensing voltage output from the pseudo data line, and is configured to compare a sensing voltage output from the data line with the reference voltage, and is configured to output a comparison result as the stored data.

12. The memory device of claim 11 , wherein the sense amplifier includes:
a precharge circuit configured to precharge the data line providing the sensing voltage, a reference line providing the reference voltage, and the pseudo data line with a power supply voltage;
a reference voltage generating circuit configured to generate the reference voltage by discharging the reference line based on a reference current and adjust an amount of the reference current based on the pseudo sensing voltage; and
a comparator configured to compare the sensing voltage with the reference voltage and output a comparison result.

13. The memory device of claim 11 , wherein one terminal of the load transistor is connected to the plurality of memory cells.

14. The memory device of claim 11 , wherein the memory cell array comprises a three-dimensional memory cell array.

15. The memory device of claim 14 , where the three-dimensional memory cell array comprises a plurality of memory strings that are perpendicular to a substrate.

16. A sense amplifier comprising:
a bias circuit configured to generate a bias voltage based on a pseudo data line, said pseudo data line is coupled to a memory cell in response to a control signal;
a discharge circuit configured to generate a reference current based on the bias voltage;
a reference line connected to the discharge circuit, said reference line configured to provide a reference voltage based on the reference current; and
a comparator configured to generate an output voltage based on the reference voltage and a sensing voltage, said comparator connected to the reference line and to a data line, said data line is coupled to the memory cell in response to the control signal and said data line different than said pseudo data line.

17. The sense amplifier of claim 16 , wherein the bias circuit includes
a current source with a first node and a second node, said first node connected to a power supply voltage,
a first PMOS transistor including a first PMOS source and a first PMOS drain, said first PMOS source connected to the second node of the current source,
a second PMOS transistor including a second PMOS source and a second PMOS drain, said second PMOS source connected to the current source,
a first NMOS transistor, including a first NMOS gate, and a first NMOS drain, and a first NMOS source, said first NMOS gate connected to the first PMOS drain, said first NMOS drain connected to said first NMOS gate, said first NMOS source connected to a ground,
a second NMOS transistor, including a second NMOS gate, and a second NMOS drain, and a second NMOS source, said second NMOS gate connected to the second PMOS drain, said second NMOS drain connected to said second NMOS gate, said second NMOS source connected to the ground.

18. The sense amplifier of claim 16 , wherein the bias circuit includes
a current source with a first node and a second node, the second node connected to a ground,
a first NMOS transistor including a first NMOS gate, and a first NMOS source, and a first NMOS drain, said first NMOS source connected to the ground, said first NMOS gate connected to the first NMOS drain,
a second NMOS transistor including a second NMOS gate, and a second NMOS source, and a se

Assignees

• Ihm Jeong Don
• Katare Siddharth
• Kim Hyun Jin
• Samsung Electronics Co Ltd

Inventors

• Ihm Jeong-Don
• Katare Siddharth
• Kim Hyun-Jin

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/28 Primary

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/067

  Single-ended amplifiers · CPC title