Array substrate, display panel and display apparatus having the same, and driving method thereof

Patent metadata

Field	Value
Publication number	US-10176360-B2
Application number	US-201615543502-A
Country	US
Kind code	B2
Filing date	Sep 27, 2016
Priority date	Jul 11, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

An array substrate includes a base substrate; an array of a plurality of pixel units on the base substrate, each pixel unit including at least one subpixel for image display, at least some of the plurality of pixel units including a semiconductor photodetector in at least one subpixel for detecting biometric information; a plurality of first scan lines for driving image display; a plurality of second scan lines, each second scan line being connected to a row of subpixels having the semiconductor photodetector in a row of pixel units; and a plurality of read lines, each read line being connected to each semiconductor photodetector in a column of subpixels having the semiconductor photodetector in a column of pixel units.

First claim

What is claimed is:

1. An array substrate for displaying a plurality of frames of image, comprising:
a base substrate;
an array of a plurality of pixel units on the base substrate, each pixel unit comprising at least one subpixel for image display, at least one of the plurality of pixel units comprising a semiconductor photodetector in at least one subpixel for detecting biometric information;
a plurality of first scan lines for driving image display;
a plurality of second scan lines, each second scan line being connected to a row of subpixels having the semiconductor photodetector in a row of pixel units; and
a plurality of read lines, each read line being connected to each semiconductor photodetector in a column of subpixels having the semiconductor photodetector in a column of pixel units;
wherein each subpixel in the plurality of pixel units comprises a first transistor for driving image display;
each semiconductor photodetector comprises a first polarity region connected to a common electrode in a same subpixel, and a second polarity region connected to an electrode configured to provide a reset voltage signal to the second polarity region, and a diode junction connecting the first polarity region and the second polarity region; and
each subpixel having the semiconductor photodetector comprises a second transistor, the second transistor comprising a gate node connected to a corresponding second scan line, a first node connected to a corresponding read line, and a second node connected to the second polarity region directly, or indirectly through the electrode configured to provide the reset voltage signal.

2. The array substrate of claim 1 , wherein the electrode configured to provide the reset voltage signal is the second node of the second transistor; the semiconductor photodetector is on a side of the second node of the second transistor distal to the base substrate; and a projection of the semiconductor photodetector in plan view of the array substrate is within a projection of the second node of the second transistor in a same subpixel.

3. The array substrate of claim 1 , wherein the electrode configured to provide the reset voltage signal is an electrode in a same layer as a pixel electrode in a same subpixel; and the semiconductor photodetector is on a side of the electrode distal to the base substrate.

4. The array substrate of claim 3 , wherein each subpixel having the semiconductor photodetector further comprises a light shield layer on a side of the electrode proximal to the base substrate; and
a projection of the semiconductor photodetector in plan view of the array substrate is within a projection of the light shield layer in a same subpixel.

5. The array substrate of claim 3 , wherein each pixel unit comprises a subpixel region and an inter-subpixel region, and a single semiconductor photodetector in each pixel unit is configured to span over portions of inter-subpixel regions of at least two subpixels in each pixel unit.

6. The array substrate of claim 3 , wherein each pixel unit comprises a subpixel region and an inter-subpixel region, and a single semiconductor photodetector in each pixel unit is configured to span over portions of inter-subpixel regions of all subpixels in each pixel unit.

7. The array substrate of claim 1 , wherein
the plurality of first scan lines is configured to drive the plurality of pixel units row-by-row in a first time period; each first scan line in the first time period of each frame of image of the plurality of frames of image is configured to apply a first scan signal to each subpixel in the row of subpixels to allow a data signal to be passed from a corresponding data line to the each subpixel in the row of subpixels to produce a subpixel of an image based on the data signal;
the plurality of second scan lines is configured to drive the plurality of pixel units row-by-row in a second time period; each second scan line in the second time period of each frame of image of the plurality of frames of image is configured to apply a second scan signal to each second transistor in the row of the subpixels to allow the reset voltage signal to be passed from a corresponding electrode configured to provide the reset voltage signal to each semiconductor photodetector; the reset voltage signal being configured to set the second polarity region of the semiconductor photodetector at a high voltage level, the common electrode being configured to apply a common voltage signal to set the first polarity region of the semiconductor photodetector at a low voltage level, and the semiconductor photodetector being configured to be in a reversely biased state; the second time period being later in time than the first time period; and
the plurality of second scan lines is configured to drive the plurality of pixel units row-by-row in a third time period; each second scan line in the third time period of each frame of image of the plurality of frames of image is configured to apply a third scan signal to each second transistor in the row of the subpixels to transmit a biometric signal from the each subpixel in the row of subpixels having the semiconductor photodetector to a corresponding read line; the third time period being later in time than the second time period.

8. The array substrate of claim 7 , wherein the plurality of second scan lines is configured to drive the plurality of pixel units simultaneously in an intermittent time period; the plurality of second scan lines in the intermittent time period of each frame of image of the plurality of frames of image is configured to apply a fourth scan signal to a plurality of second transistors in the plurality of pixel units simultaneously to transmit a plurality of biometric signals from the plurality of subpixels having the semiconductor photodetector to a plurality of corresponding read lines; and a sum of the biometric signal from each read line forms a cumulative biometric signal.

9. The array substrate of claim 8 , wherein the intermittent time period is earlier in time than the second time period.

10. The array substrate of claim 8 , wherein the plurality of second scan lines in the intermittent time period of each frame of image of the plurality of frames of image is configured to apply the fourth scan signal multiple times.

11. The array substrate of claim 7 , wherein each data line connected to the column of subpixels having the semiconductor photodetector is used as a read line for the column of subpixels having the semiconductor photodetector in the third time period, and used as a data line in the first time period.

12. The array substrate of claim 1 , wherein the semiconductor photodetector is a PN photodiode, the first polarity region is a P+doping semiconductor region, and the second polarity region is an N+doping semiconductor region.

13. The array substrate of claim 1 , wherein the semiconductor photodetector is a PIN photodiode, the first polarity region is a P+doping semiconductor region, the second polarity region is an N+doping semiconductor region, and the PIN photodiode further comprises an intrinsic region of amorphous silicon between the P+doping semiconductor region and the N+doping semiconductor region.

14. The array substrate of claim 1 , wherein each pixel unit comprises a subpixel region and an inter-subpixel region, and the semiconductor photodetector is within the inter-subpixel region.

15. A display panel, comprising the array substrate of claim 1 .

16. A display apparatus, comprising the display panel of claim 15 .

17. A method for driving an operation of an array sub

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Liu Yingming
• Dong Xue
• Xue Hailin
• Chen Xiaochuan
• Ding Xiaoliang
• Yang Shengji
• Wang Haisheng
• Xu Rui
• Li Changfeng
• Liu Wei
• Wang Pengpeng

Classifications

• G06F3/041

  Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means · CPC title

• G09G2310/0278

  Details of driving circuits arranged to drive both scan and data electrodes · CPC title

• G09G3/36

  using liquid crystals · CPC title

• H01L31/02024

  Electricity · mapped topic

• G06K9/0002 Primary

  Physics · mapped topic