Gathering and scattering multiple data elements

Patent metadata

Field	Value
Publication number	US-10175990-B2
Application number	US-201313898189-A
Country	US
Kind code	B2
Filing date	May 20, 2013
Priority date	Dec 22, 2009
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

First claim

What is claimed is:

1. A processor comprising:
a decoder stage to decode a single instruction for accessing data elements at a plurality of non-register memory locations; and
at least one execution unit, coupled to the decode stage to receive the decoded instruction and responsive to the decoded instruction, to:
issue accesses to at least one of the plurality of memory locations;
detect when any exceptions occur due to the accesses to the at least of the plurality of non-register memory locations;
store accessed data elements that do not have exceptions; and
handle any pending interrupts upon completion of the single instruction.

2. The processor of claim 1 , the one or more execution units further to:
detect if any traps or interrupts occur; and
record detected traps or interrupts as pending traps or interrupts.

3. The processor of claim 2 wherein detecting if any traps or interrupts occur includes detecting any breakpoints.

4. The processor of claim 3 , the one or more execution units further to:
set a flag in response to said handling of any traps or interrupts.

5. The processor of claim 4 , the one or more execution units further to:
not handle a pending breakpoint upon said completion of the single instruction, or detection of a fault or an exception, whenever the flag has been set.

6. The processor of claim 5 wherein the flag is an EFLAG.RF.

7. The processor of claim 2 , the one or more execution units further to:
clear any corresponding state elements in a mask register.

8. The processor of claim 2 , the one or more execution units further to:
store the data elements at the plurality of memory locations of an addressable memory; and
clear any corresponding state elements in a mask register.

9. A processor comprising:
a decoder stage to decode a single instruction for accessing data elements at a plurality of non-register memory locations; and
at least one execution unit, coupled to the decoder to receive the decoded instruction and responsive to the decoded instruction, to:
issue accesses to at least one of the plurality of memory locations;
detect when any interrupts occur;
record detected traps or interrupts as pending interrupts;
detect when any exceptions occur due to the accesses to the at least of the plurality of memory locations; and
handle any pending interrupts upon completion of the single instruction.

10. The processor of claim 9 wherein detecting if any traps or interrupts occur includes detecting if any breakpoints occur.

11. The processor of claim 9 , the one or more execution units further to:
set a flag in response to said handling of any traps or interrupts.

12. The processor of claim 11 wherein the flag is an EFLAG.RF.

13. The processor of claim 10 , the one or more execution units further to:
store the data elements in a destination register; and
clear any corresponding state elements in a mask register.

14. The processor of claim 10 , the one or more execution units further to:
store the data elements at the plurality of memory locations of an addressable memory; and
clear any corresponding state elements in a mask register.

15. A method comprising:
decoding a single instruction for accessing data elements at a plurality of non-register memory locations; and
receiving the decoded instruction in at least one execution unit and responsive to receiving the decoded instruction:
issuing accesses to at least one of the plurality of memory locations;
detecting when any faults or exceptions occur due to the accesses to the at least of the plurality of memory locations;
storing accessed data elements that do not have exceptions; and
handling any pending interrupts upon completion of the single instruction.

16. The method of claim 15 , further responsive to receiving said decoded instruction, the one or more execution units:
detecting if any traps or interrupts occur; and
recording detected traps or interrupts as pending traps or interrupts.

17. The method of claim 16 wherein detecting if any traps or interrupts occur includes detecting any breakpoints.

18. The method of claim 17 , further responsive to receiving said decoded instruction, the one or more execution units:
setting a flag in response to said handling of any traps or interrupts.

19. The method of claim 18 , further responsive to receiving said decoded instruction, the one or more execution units:
not handling a pending breakpoint upon said completion of the single instruction, or detection of a fault or an exception, whenever the flag has been set.

20. The method of claim 19 wherein the flag is an EFLAG.RF.

21. The method of claim 19 , further responsive to receiving said decoded instruction, the one or more execution units:
storing the data elements at the plurality of memory locations of an addressable memory; and
clearing any corresponding state elements in a mask register.

22. A system comprising:
a memory controller coupled to a plurality of memory locations; and
a processor coupled to the memory controller, the processor comprising:
a decoder stage to decode a single instruction for accessing data elements at the plurality of non-register memory locations; and
at least one execution unit, coupled to the decoder to receive the decoded instruction and responsive to the decoded instruction, to:
issue accesses to at least one of the plurality of memory locations;
detect when any exceptions occur due to the accesses to the at least of the plurality of memory locations;
store accessed data elements that do not have exceptions; and
handle any pending interrupts upon completion of the single instruction.

23. The system of claim 22 , the one or more execution units further to:
detect if any traps or interrupts occur; and
record detected traps or interrupts as pending traps or interrupts.

24. The system of claim 23 wherein detecting if any traps or interrupts occur includes detecting any breakpoints.

25. The system of claim 24 , the one or more execution units further to:
store the data elements in a destination register; and
clear any corresponding state elements in a mask register.

Assignees

• Intel Corp

Inventors

• Hughes Christopher J
• Chen Yen-Kuang (Y K )
• Bomb Mayank
• Brandt Jason W
• Buxton Mark J
• Charney Mark J
• Chennupaty Srinivas
• Corbal Jesus
• Dixon Martin G
• Girkar Milind B
• Hall Jonathan C
• Ido Hideki (Saito)
• Lachner Peter
• Neiger Gilbert
• Newburn Chris J
• Parthasarathy Rajesh S
• Toll Bret L
• Valentine Robert
• Wiedemeier Jeffrey G

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3861 Primary

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/345

  of multiple operands or results {(addressing multiple banks G06F12/06)} · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title