Elimination method of parasitic capacitance and device

Patent metadata

Field	Value
Publication number	US-10175812-B2
Application number	US-201615300254-A
Country	US
Kind code	B2
Filing date	Aug 12, 2016
Priority date	Aug 3, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

The disclosure discloses an elimination method of parasitic capacitance and a device. During a touch scanning period, inputting a first simulation signal to source electrode lines and inputting a second simulation signal to multiplex lines can eliminate parasitic capacitance. Waveforms of the first simulation signal and a touch scanning signal input in a common electrode are identical or similar, waveforms of the second simulation signal and the touch scanning signal input in the common electrode are similar, waveforms of the third simulation signal and the touch scanning signal input in the common electrode are similar, a second simulation waveform includes a first target high level, a second target high level, a first target low level and a second target low level that are generated by different modules, the first target high level>the second target high level>the first target low level>the second target low level.

First claim

What is claimed is:

1. An elimination method of parasitic capacitance, wherein the touch display panel comprises a plurality of gate lines, a plurality of source electrode lines, a plurality of common electrode lines, a plurality of multiplex lines, an extension direction of the plurality of common electrode lines and an extension direction of the source electrode lines are parallel, a common electrode comprises a plurality of sensor pads, the common electrode is multiplexed to be a touch driving electrode, the plurality of common electrode lines are connected to the plurality of sensor pads respectively, the plurality of multiplex lines are connected to the plurality of gate lines respectively, a scanning cycle comprises a display scanning period and a touch scanning period,
during the touch scanning period, inputting a first simulation signal to the plurality of source electrode lines, inputting a second simulation signal to the plurality of multiplex lines and inputting a third simulation signal to the plurality of gate lines for eliminating parasitic capacitance formed among the plurality of gate lines, the plurality of source electrode lines, the plurality of common electrode lines and the plurality of sensor pads;
wherein a waveform of the first simulation signal and a waveform of a scanning signal input in the common electrode are similar, a waveform of the second simulation signal and the waveform of the scanning signal input in the common electrode are similar, a waveform of the third simulation signal and the waveform of the scanning signal input in the common electrode are similar.

2. The method according to claim 1 , wherein the waveform of the second simulation signal comprises a first target high level and a second target high level, the waveform of the second simulation signal comprises a first target low level and a second target low level, the first target high level and the second target high level are generated by different VGH modules, the first target low level and the second target low level are generated by different VGL modules.

3. The method according to claim 2 , wherein the first target high level is generated by a first VGH module, the second target high level is generated by a second VGH module, the first target low level is generated by a first VGL module, the second target low level is generated by a second VGL module.

4. The method according to claim 2 , wherein the first target high level>the second target high level>the first target low level>the second target low level.

5. The method according to claim 1 , wherein the waveform of the first simulation signal and the waveform of the scanning signal input in the common electrode are identical.

6. An elimination device of parasitic capacitance, wherein the touch display panel comprises a plurality of gate lines, a plurality of source electrode lines, a plurality of common electrode lines, a plurality of multiplex lines, an extension direction of the plurality of common electrode lines and an extension direction of the source electrode lines are parallel, a common electrode comprises a plurality of sensor pads, the common electrode is multiplexed to be a touch driving electrode, the plurality of common electrode lines are connected to the plurality of sensor pads respectively, the plurality of multiplex lines are connected to the plurality of gate lines respectively, a scanning cycle comprises a display scanning period and a touch scanning period, the device comprises a first input circuit, a second input circuit and a third input circuit,
a first input circuit being configured to input a first simulation signal to the plurality of source electrode lines during the touch scanning period, the second input circuit being configured to input a second simulation signal to the plurality of multiplex lines, the third input circuit being configured to input a third simulation signal to the plurality of gate lines, so as to eliminate parasitic capacitance formed among the plurality of gate lines, the plurality of source electrode lines, the plurality of common electrode lines and the plurality of sensor pads;
wherein a waveform of the first simulation signal and a waveform of a scanning signal input in the common electrode are similar, a waveform of the second simulation signal and the waveform of the scanning signal input in the common electrode are similar, a waveform of the third simulation signal and the waveform of the scanning signal input in the common electrode are similar.

7. The device according to claim 6 , wherein the waveform of the second simulation signal comprises a first target high level and a second target high level, the waveform of the second simulation signal comprises a first target low level and a second target low level, the first target high level and the second target high level are generated by different VGH modules, the first target low level and the second target low level are generated by different VGL modules.

8. The device according to claim 7 , wherein the first target high level is generated by a first VGH module, the second target high level is generated by a second VGH module, the first target low level is generated by a first VGL module, the second target low level is generated by a second VGL module.

9. The device according to claim 8 , wherein the first target high level>the second target high level>the first target low level>the second target low level.

10. The device according to claim 7 , wherein the waveform of the first simulation signal and the waveform of the scanning signal input in the common electrode are identical.

Assignees

• Wuhan China Star Optoelectronics Technology Co Ltd
• Wuhan China Star Optoelectronics Technology Co Ltd

Inventors

• Ji Feilin
• Tan Xiaoping

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G06F3/0416 Primary

  Control or interface arrangements specially adapted for digitisers · CPC title

• G06F3/0412 Primary

  Digitisers structurally integrated in a display · CPC title

• G06F3/0418 Primary

  for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title