Receiving circuit, electronic device, transmission/reception system, and receiving circuit control method

Patent metadata

Field	Value
Publication number	US-10171228-B2
Application number	US-201615554362-A
Country	US
Kind code	B2
Filing date	Feb 2, 2016
Priority date	Mar 19, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

In a self-synchronous transmission scheme, received data is accurately acquired. A timing signal generating unit generates timing signals indicating different timings in synchronization with a timing at which a status of a reception signal transitions. A first data signal generating unit generates a first data signal from statuses of the reception signal before and after a timing at which a predetermined first timing signal becomes a specific value, and outputs the first data signal in synchronization with a second timing signal different from the first timing signal. A second data signal generating unit generates a second data signal from statuses of the reception signal before and after a timing at which the second timing signal becomes the specific value, and outputs the second data signal in synchronization with a timing signal different from the first timing signal.

First claim

The invention claimed is:

1. A receiving circuit comprising:
a timing signal generating unit that generates a plurality of timing signals indicating different timings in synchronization with a timing at which a status of a reception signal transitions;
a first data signal generating unit that generates, each time a predetermined first timing signal among the plurality of timing signals becomes a specific value, a first data signal from statuses of the reception signal before and after a timing at which the predetermined first timing signal becomes the specific value, and outputs the first data signal in synchronization with a second timing signal different from the first timing signal among the plurality of timing signals; and
a second data signal generating unit that generates, each time the second timing signal becomes the specific value, a second data signal from statuses of the reception signal before and after timing at which the second timing signal becomes the specific value, and outputs the second data signal in synchronization with a timing signal different from the first timing signal among the plurality of timing signals.

2. The receiving circuit according to claim 1 , further comprising
a separating unit that separates the statuses of the reception signal into a first status just before the first timing signal becomes the specific value and a second status just before the second timing signal becomes the specific value,
wherein the first data signal generating unit generates data indicating a transition pattern from the first status to the second status as the first data signal, and
the second data signal generating unit generates data indicating a transition pattern from the second status to the first status as the second data signal.

3. The receiving circuit according to claim 1 ,
wherein the timing signal generating unit includes
a binary counter circuit that counts a 1-bit counter value each time the reception signal transitions and outputs a signal of the counter value as the first timing signal, and
a second timing signal generating circuit that generates a signal obtained by inverting the first timing signal as the second timing signal.

4. The receiving circuit according to claim 1 , further comprising
a third data signal generating unit that generates, each time a third timing signal different from the first and second timing signals among the plurality of timing signals becomes a specific value, a third data signal from statuses of the reception signal before and after a timing at which the third timing signal becomes the specific value, and outputs the third data signal in synchronization with the first timing signal,
wherein the second data signal generating unit outputs the second data signal in synchronization with the third timing signal.

5. The receiving circuit according to claim 4 ,
wherein the clock signal generating unit includes a senary counter circuit that counts a 3-bit counter value each time the status transitions, separates the counter value into the first, second, and third timing signals, and outputs the first, second, and third timing signals.

6. The receiving circuit according to claim 3 ,
wherein the binary counter circuit includes
a plurality of latch circuits associated with different statuses, and
a multiplexer,
each of the plurality of latch circuits holds an inverted signal obtained by inverting a feedback signal in a case where the reception signal transitions to the corresponding status, and
the multiplexer inverts the held inverted signal, feeds the held inverted signal back to the plurality of latch circuits as a new feedback signal, and outputs the new feedback signal as the first timing signal.

7. The receiving circuit according to claim 1 , further comprising:
a third data signal generating unit that generates, each time a third timing signal different from the first and second timing signals among the plurality of timing signals becomes a specific value, a third data signal from statuses of the reception signal before and after a timing at which the third timing signal becomes the specific value, and outputs the third data signal in synchronization with a fourth timing signal different from the first, second, and third timing signals among the plurality of timing signals; and
a fourth data signal generating unit that generates, each time the fourth timing signal becomes a specific value, a fourth data signal from statuses of the reception signal before and after a timing at which the fourth timing signal becomes the specific value, and outputs the fourth data signal in synchronization with the first timing signal,
wherein the second data signal generating unit outputs the second data signal in synchronization with the third timing signal.

8. The receiving circuit according to claim 7 ,
wherein the timing signal generating unit includes
a quaternary counter circuit that counts a 2-bit counter value each time the reception signal transitions, and
a counter value decoder that analyzes the counter value and generates the first, second, third, and fourth timing signals on the basis of an analysis result.

9. An electronic device, comprising:
a receiving circuit that generates a plurality of timing signals indicating different timings in synchronization with a timing at which a status of a reception signal transitions; and
a processing circuit including a first data signal generating unit that generates, each time a predetermined first timing signal among the plurality of timing signals becomes a specific value, a first data signal from statuses of the reception signal before and after a timing at which the predetermined first timing signal becomes the specific value, and outputs the first data signal in synchronization with a second timing signal different from the first timing signal among the plurality of timing signals, and a second data signal generating unit that generates, each time the second timing signal becomes the specific value, a second data signal from statuses of the reception signal before and after timing at which the second timing signal becomes the specific value, and outputs the second data signal in synchronization with a timing signal different from the first timing signal among the plurality of timing signals.

10. The electronic device according to claim 9 ,
wherein the receiving circuit includes
a timing signal generating unit that generates the plurality of timing signals, and
a separating unit that separates statuses of the reception signal into a first status just before the first timing signal becomes the specific value and a second status just before the second timing signal becomes the specific value,
the first data signal generating unit generates data indicating a transition pattern from the first status to the second status as the first data signal, and
the second data signal generating unit generates data indicating a transition pattern from the second status to the first status as the second data signal.

11. The electronic device according to claim 10 ,
wherein the separating unit includes
a first latch circuit that holds a signal obtained by inverting a previous feedback signal each time the status of the reception signal transitions to the first status and outputs the held value as an output signal,
a second latch circuit that holds a signal obtained by inverting the previous output signal each time the status of the reception signal transitions to the second status, and outputs the held value as the feedback signal,
a first inverting unit that outputs a signal obtained by inverting the output signal as first status data indicating the first status, and
a second inve

Assignees

• Sony Corp

Inventors

• Hosaka Hajime

Classifications

• H04L25/02

  Details {; arrangements for supplying electrical power along data transmission lines (systems for transmitting signals via power distribution lines H04B3/54)} · CPC title

• H04L7/00

  Arrangements for synchronising receiver with transmitter {(synchronisation of generators of electric oscillations or pulses H03L7/00)} · CPC title

• H04L7/0079 Primary

  Receiver details · CPC title

• H04L25/49 Primary

  using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} · CPC title