Analog-to-digital converter (ADC) with improved power disturbance reduction

Patent metadata

Field	Value
Publication number	US-10171098-B2
Application number	US-201715817555-A
Country	US
Kind code	B2
Filing date	Nov 20, 2017
Priority date	Nov 23, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Disclosed herein is an analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising a first node of the input analog voltage; nodes of a plurality of reference voltages; a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage of the plurality of reference voltages; a logic circuit block for receiving outputs of the plurality of comparators and generating the output digital code; and a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages.

First claim

What is claimed is:

1. An analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising:
a first node of the input analog voltage;
nodes of a plurality of reference voltages;
a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage among the plurality of reference voltages;
a logic circuit block adapted to receive outputs of the plurality of comparators and generating the output digital code; and
a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages,
wherein the voltage stabilizer is configured to reduce a phase difference between a first disturb on the input analog voltage of the first node and a second disturb on the node of the first reference voltage.

2. The ADC of claim 1 , wherein the voltage stabilizer comprises a first capacitor.

3. The ADC of claim 2 , wherein the ADC is adapted to determine the first reference voltage among the plurality of reference voltages, the first reference voltage being the closest to the input analog voltage at the first node, and wherein the ADC is adapted to couple terminals of the first capacitor with the first node and the node of the first reference voltage.

4. The ADC of claim 3 , wherein a voltage level of the first reference voltage is higher than a voltage level of the input analog voltage at the first node.

5. The ADC of claim 3 , wherein a voltage level of the first reference voltage is lower than a voltage level of the input analog voltage at the first node.

6. The ADC of claim 2 , further comprising: a second capacitor, a second reference voltage being selected to be coupled with the second capacitor from the plurality of the reference voltages.

7. The ADC of claim 6 , wherein the ADC is adapted to determine the first reference voltage among the plurality of reference voltages, a voltage level of the first reference voltage being greater than a voltage level of the input analog voltage at the first node,
wherein the ADC is adapted to determine the second reference voltage among the plurality of reference voltages, a voltage level of the second reference voltage being smaller than a voltage level of the input analog voltage at the first node, and
wherein the ADC is adapted to couple terminals of the first capacitor with the first node and the node of the first reference voltage and is adapted to couple terminals of the second capacitor with the first node and a node of the second reference voltage.

8. The ADC of claim 7 , wherein the first reference voltage is the closest higher reference voltage to the input analog voltage at the first node, and the second reference voltage is the closest lower reference voltage to the input analog voltage at the first node.

9. The ADC of claim 2 , wherein the voltage stabilizer further comprises more than two capacitors comprising the first capacitor, and wherein the ADC is adapted to couple terminals of each of the capacitors with the first node and a node of a corresponding reference voltage of the plurality of reference voltages.

10. The ADC of claim 9 , wherein a number of the capacitors coupled with the first node is odd.

11. The ADC of claim 9 , wherein a number of the capacitors coupled with the first node is even.

12. The ADC of claim 9 , wherein the ADC is adapted to couple terminals of each of a first group of the capacitors with the first node and each of a first group of the reference voltages, voltage levels of the first group of reference voltages being higher than a voltage value of the input analog voltage at the first node, and
wherein the ADC is adapted to couple terminals of each of a second group of the capacitors with the first node and each of a second group of the reference voltages, voltage levels of the second group of reference voltages being lower than the voltage value of the input analog voltage at the first node.

13. The ADC of claim 12 , wherein the first group of reference voltages is symmetrical to the second group of reference voltages with respect to the input analog voltage.

14. The ADC of claim 12 , wherein the reference voltages of the first group are the closest higher reference voltages to the input analog voltage at the first node, and the reference voltages of the second group are the closest lower reference voltages to the input analog voltage at the first node.

15. The ADC of claim 2 , further comprising: a reference voltage selection circuit block adapted to receive the output digital code and selecting the first reference voltage to be coupled with the first capacitor from the plurality of reference voltages.

16. The ADC of claim 15 , wherein the voltage stabilizer further comprises a second capacitor, and wherein the reference voltage selection circuit block is adapted to select a second reference voltage to be coupled with a second capacitor from the plurality of reference voltages.

17. The ADC of claim 16 , wherein the reference voltage selection circuit block comprises:
an even reference multiplexer adapted to receive a plurality of even reference voltages from among the reference voltages;
an odd reference multiplexer adapted to receive a plurality of odd reference voltages from among the reference voltages; and
a selection block adapted to generate an even reference selection signal to be provided to the even reference multiplexer and an odd reference selection signal to be provided to the odd reference multiplexer,
wherein an output of the even reference multiplexer is coupled to the first capacitor, and an output of the odd reference multiplexer is coupled to the second capacitor.

18. An analog-to-digital converter (ADC), comprising:
an input node suitable for receiving an analog signal;
a comparator suitable for receiving the analog signal at a first input and a reference voltage at a second input and for outputting a result based on comparison of the analog signal and the reference voltage, the comparator comprising a capacitive stabilizer connected to the first input and the second input in common; and
an output node suitable for outputting a digital signal based on the result output from the comparator,
wherein the capacitive stabilizer is configured to reduce a phase difference between a first disturb on the analog signal at the first input and a second disturb on the reference voltage at the second input.

Assignees

• Sk Hynix Inc

Inventors

• Paone Luigi
• Passerini Marco

Classifications

• G01K2219/00

  Thermometers with dedicated analog to digital converters · CPC title

• H03M1/0845 Primary

  of power supply variations, e.g. ripple · CPC title

• H03M1/36

  simultaneously only, i.e. parallel type · CPC title

• G01K13/00

  Thermometers specially adapted for specific purposes · CPC title

• H03M1/361

  having a separate comparator and reference value for each quantisation level, i.e. full flash converter type · CPC title