Operational amplifier and differential amplifying circuit thereof

Patent metadata

Field	Value
Publication number	US-10171052-B2
Application number	US-201715818547-A
Country	US
Kind code	B2
Filing date	Nov 20, 2017
Priority date	Nov 29, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

An operational amplifier and a differential amplifying circuit thereof. The differential amplifying circuit receives a differential input signal and outputs a differential output signal. The differential amplifying circuit includes an output port that has a first terminal and a second terminal, the differential output signal being outputted via the first and second terminals; a first transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; a second transistor pair receiving the differential input signal via two first ends and coupling to the first and second terminals respectively via two second ends; and a third transistor pair receiving a control signal via two first ends and coupling to the first and second terminals respectively via two second ends. The control signal controls the third transistor pair to switch on or off and/or controls the current flowing therethrough.

First claim

What is claimed is:

1. An operational amplifier, having a differential input pair and a differential output pair, comprising:
an output stage amplifying circuit, using a first terminal and a second terminal as an input port thereof and using said differential output pair as an output port thereof;
a first transistor pair, comprising a first transistor and a second transistor, wherein a first end of said first transistor and a first end of said second transistor are respectively coupled to a first input end and a second input end of said differential input pair, and a second end of said first transistor and a second end of said second transistor are respectively coupled to said first terminal and said second terminal;
a second transistor pair, comprising a third transistor and a fourth transistor, wherein a first end of said third transistor and a first end of said fourth transistor are respectively coupled to said first input end and said second input end of said differential input pair, and a second end of said third transistor and a second end of said fourth transistor are respectively coupled to said first terminal and said second terminal;
a first current source, coupled to said first terminal;
a second current source, coupled to said second terminal;
a third transistor pair, comprising a fifth transistor and a sixth transistor, wherein a first end of said fifth transistor and a first end of said sixth transistor respectively receive a control signal, and a second end of said fifth transistor and a second end of said sixth transistor are respectively coupled to said first terminal and said second terminal; and
a control circuit, coupled to said differential output pair, for generating said control signal according to voltages of said differential output pair and a common mode voltage.

2. The operational amplifier of claim 1 , wherein said operational amplifier receives a differential input signal through said differential input pair and outputs a differential output signal through said differential output pair, said fifth transistor and said sixth transistor are nMOSFETs, and when an average of said differential output signal is substantially smaller than said common mode voltage, said control circuit increases a voltage of said control signal to increase the electric current flowing through said third transistor pair, so as to reduce the electric potentials of said first terminal and said second terminal.

3. The operational amplifier of claim 1 , wherein said operational amplifier receives a differential input signal through said differential input pair and outputs a differential output signal through said differential output pair, said fifth transistor and said sixth transistor are pMOSFETs, and when an average of said differential output signal is substantially greater than said common mode voltage, said control circuit decreases a voltage of said control signal to increase the electric current flowing through said third transistor pair, so as to increase the electric potentials of said first terminal and said second terminal.

4. The operational amplifier of claim 1 further comprising:
a third current source;
wherein, a third end of said third transistor and a third end of said fourth transistor are coupled to a reference voltage through said third current source, and a third end of said fifth transistor and a third end of said sixth transistor are coupled to said reference voltage through said third current source.

5. The operational amplifier of claim 4 , wherein a magnitude of an electric current of said third current source is controlled by said control signal.

6. The operational amplifier of claim 1 further comprising:
a third current source;
wherein, a third end of said third transistor and a third end of said fourth transistor are coupled to a reference voltage through said third current source, a third end of said fifth transistor and a third end of said sixth transistor are coupled to said reference voltage, and said third current source is not coupled between said reference voltage and said third ends of said fifth transistor and said sixth transistor.

7. A differential amplifying circuit, receiving a differential input signal and outputting a differential output signal, comprising:
an output port, having a first terminal and a second terminal, wherein said differential output signal is outputted via said first terminal and said second terminal;
a first transistor pair, comprising a first transistor and a second transistor, wherein a first end of said first transistor and a first end of said second transistor receive said differential input signal, and a second end of said first transistor and a second end of said second transistor are respectively coupled to said first terminal and said second terminal;
a second transistor pair, comprising a third transistor and a fourth transistor, wherein a first end of said third transistor and a first end of said fourth transistor receive said differential input signal, and a second end of said third transistor and a second end of said fourth transistor are respectively coupled to said first terminal and said second terminal; and
a third transistor pair, comprising a fifth transistor and a sixth transistor, wherein a first end of said fifth transistor and a first end of said sixth transistor respectively receive a control signal, and a second end of said fifth transistor and a second end of said sixth transistor are respectively coupled to said first terminal and said second terminal;
wherein, said control signal controls said fifth transistor and said sixth transistor to turn on or off and/or controls the electric currents flowing therethrough.

8. The differential amplifying circuit of claim 7 , wherein said fifth transistor and said sixth transistor are nMOSFETs, and when an average of said differential output signal is substantially smaller than a common mode voltage, said control signal causes the electric currents flowing through said third transistor pair to increase, so as to decrease the electric potentials of said first terminal and said second terminal.

9. The differential amplifying circuit of claim 7 , wherein said fifth transistor and said sixth transistor are pMOSFETs, and when an average of said differential output signal is substantially greater than a common mode voltage, said control signal causes the electric currents flowing through said third transistor pair to increase, so as to increase the electric potentials of said first terminal and said second terminal.

10. The differential amplifying circuit of claim 7 further comprising:
a current source;
wherein, a third end of said third transistor and a third end of said fourth transistor are coupled to a reference voltage through said current source, and a third end of said fifth transistor and a third end of said sixth transistor are coupled to said reference voltage through said current source.

11. The differential amplifying circuit of claim 10 , wherein a magnitude of the electric current of said current source is controlled by said control signal.

12. The differential amplifying circuit of claim 7 further comprising:
a current source;
wherein, a third end of said third transistor and a third end of said fourth transistor are coupled to a reference voltage through said current source, a third end of said fifth transistor and a third end of said sixth transistor are coupled to said reference voltage, and said current source is not coupled between said reference voltage and said third ends of said fifth transistor and said sixth transistor.

Assignees

• Realtek Semiconductor Corp

Inventors

• Shih Kuan-Yu

Classifications

• H03F2200/48

  the output of the amplifier being coupled out by a capacitor · CPC title

• H03F2200/267

  A capacitor based passive circuit, e.g. filter, being used in an amplifying circuit · CPC title

• H03F3/45636

  by using feedback means (H03F3/45744 takes precedence) · CPC title

• H03F3/4565

  Controlling the common source circuit of the differential amplifier · CPC title

• H03F2200/144

  the feedback circuit of the amplifier stage comprising a passive resistor and passive capacitor · CPC title