Reduction of audible noise in a power converter

Patent metadata

Field	Value
Publication number	US-10171000-B2
Application number	US-201815979247-A
Country	US
Kind code	B2
Filing date	May 14, 2018
Priority date	Feb 26, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A power converter controller includes a drive circuit to generate a drive signal to control switching of a power switch. The drive circuit generates the drive signal in response to a current sense signal, a current limit signal, a frequency skip signal, and a hold signal. A current limit generator generates the current limit signal in response to a load. A frequency detection circuit generates the frequency skip signal in response to the drive signal to indicate when an intended frequency of the drive signal is within a frequency window. The current limit signal remains fixed for at least a switching cycle when the intended frequency is within the frequency window. A first latch generates the hold signal to control the current limit generator to hold the current limit signal. The first latch generates the hold signal in response to the frequency skip signal and a feedback signal.

First claim

What is claimed is:

1. A controller for use in a power converter, comprising:
a drive circuit coupled to generate a drive signal to control switching of a power switch of the power converter to control a transfer of energy from an input of the power converter to the output of the power converter, wherein the drive circuit generates the drive signal in response to a current sense signal representative of a current through the power switch, a current limit signal, a frequency skip signal, and a hold signal;
a current limit generator coupled to generate the current limit signal in response to a load coupled to the output of the power converter;
a frequency detection circuit coupled to generate the frequency skip signal in response to the drive signal to indicate when an intended frequency of the drive signal is within a frequency window such that the current limit signal is coupled to remain fixed for at least a switching cycle when the frequency skip signal indicates that the intended frequency of the drive signal is within the frequency window; and
a first latch coupled to generate the hold signal to control the current limit generator to hold the current limit signal, wherein the first latch is coupled to generate the hold signal in response to the frequency skip signal, and in response to a feedback signal representative of the output of the power converter.

2. The controller of claim 1 , further comprising:
a second latch coupled to generate a pause signal coupled to control the current limit generator to latch the current limit signal, wherein the second latch is coupled to generate the pause signal in response to the frequency skip signal and in response to the feedback signal representative of the output of the power converter;
a first logic gate having an output coupled to be received by the first latch and the second latch, wherein the first logic gate has a first input coupled to receive the frequency skip signal generated by the frequency detection circuit, wherein the first logic gate has a second input coupled to be responsive to the feedback signal representative of the output of the power converter;
a second logic gate having a first input coupled to receive an output of the first latch, wherein the second logic gate has a second input coupled to be responsive to the feedback signal representative of the output of the power converter; and
a third logic gate having an output coupled to be received by the drive circuit, wherein the third logic gate has a first input coupled to receive an output of the second logic gate, wherein the third logic gate has a second input coupled to be responsive to the frequency skip signal.

3. The controller of claim 1 , wherein the frequency detection circuit comprises:
a third latch coupled to be set in response to the drive signal;
a first frequency threshold circuit coupled to be responsive to an output of the third latch to output a first frequency signal to indicate whether a pulse of the drive signal has been detected at a frequency above a first threshold frequency;
a second frequency threshold circuit coupled to be responsive to the output of the third latch to output a second frequency signal to indicate whether the pulse of the drive signal has been detected at a frequency below a second threshold frequency; and
a fourth logic gate coupled to generate the frequency skip signal in response to the first frequency threshold circuit and the second frequency threshold circuit to indicate that the frequency of the drive signal is within the frequency window, wherein the frequency window is between the first threshold frequency and the second threshold frequency.

4. The controller of claim 3 , wherein the third latch is coupled to be reset in response to the first frequency threshold circuit and the second frequency threshold circuit.

5. The controller of claim 3 , wherein the first frequency threshold circuit comprises:
a first current source;
a first capacitor;
a first switch coupled between the first current source and the first capacitor, wherein the first switch is coupled to be switched on and off in response to the output of the third latch;
a second switch coupled between a first end of the first capacitor and a second end of the first capacitor;
a first inverter coupled between the second switch and the output of the third latch, wherein the second switch is coupled to be switched on and off in response to an output of the first inverter; and
a first comparator coupled to the first capacitor to output the first frequency signal in response to a first comparison of a voltage across the first capacitor with a first voltage reference.

6. The controller of claim 5 wherein the second frequency threshold circuit comprises:
a second current source;
a second capacitor;
a third switch coupled between the second current source and the second capacitor, wherein the third switch is coupled to be switched on and off in response to the output of the third latch;
a fourth switch coupled between a first end of the second capacitor and a second end of the second capacitor;
a second inverter coupled between the fourth switch and the output of the third latch, wherein the fourth switch is coupled to be switched on and off in response to an output of the second inverter; and
a second comparator coupled to the second capacitor to output the second frequency signal in response to a second comparison of a voltage across the second capacitor with a second voltage reference.

7. The controller of claim 6 , wherein a size of the first capacitor is smaller than a size of the second capacitor.

8. The controller of claim 1 , wherein the current limit signal is coupled to remain fixed for a maximum of four switching cycles.

9. The controller of claim 1 , wherein the frequency skip signal transitions from a logic low state to a logic high state in response to a time after the drive signal reaching a period of a maximum audible noise frequency, and from the logic high state to the logic low state in response to the time after the drive signal reaching a period of a minimum audible noise frequency.

10. A power converter, comprising:
an energy transfer element coupled between an input of the power converter and an output of the power converter;
a power switch coupled to the energy transfer element and the input of the power converter;
a sense circuit coupled to generate a feedback signal representative of the output of the power converter; and
a controller coupled to the power switch, wherein the controller includes:
a drive circuit coupled to generate a drive signal to control switching of a power switch of the power converter to control a transfer of energy from an input of the power converter to the output of the power converter, wherein the drive circuit generates the drive signal in response to a current sense signal representative of a current through the power switch, a current limit signal, a frequency skip signal, and a hold signal;
a current limit generator coupled to generate the current limit signal in response to a load coupled to the output of the power converter;
a frequency detection circuit coupled to generate the frequency skip signal in response to the drive signal to indicate when an intended frequency of the drive signal is within a frequency window such that the current limit signal is coupled to remain fixed for at least a switching cycle when the frequency skip signal indicates that the intended frequency of the drive signal is within the frequency window; and
a first latch coupled to generate the hold signal to control the current limit generator to hold the current limit signal, wherein the first latch is coupled to generate the hold sign

Assignees

• Power Integrations Inc

Inventors

• Balakrishnan Vikram
• Pham Giao Minh
• Pregitzer Ricardo Luis Janezic
• Vaughan Peter

Classifications

• H02M3/335

  using semiconductor devices only · CPC title

• H02M2001/0032

  Electricity · mapped topic

• H02M3/33515 Primary

  with digital control · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title