Battery protecting apparatus

Patent metadata

Field	Value
Publication number	US-10170919-B2
Application number	US-201715622272-A
Country	US
Kind code	B2
Filing date	Jun 14, 2017
Priority date	Aug 12, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A battery protecting apparatus includes: a charging/discharging control chip including a charging control FET and a discharging control FET connected to a secondary battery; a protecting chip configured to control, based on a voltage between both ends of the secondary battery, the FETs to prevent overcharging, over discharging, and an overcurrent; and a lead frame having a connection surface for a plurality of external terminals and another surface in conduction with the connection surface. Said another surface is electrically connected, via a conductive material, to terminals of the FETs formed on a front surface of the charging/discharging control chip. A back surface of the protecting chip faces a back surface of the charging/discharging control chip via an insulative member. Terminals of the protecting chip are electrically connected to said another surface through bonding wires. The charging/discharging control chip and the protecting chip are covered by a resin.

First claim

What is claimed is:

1. A battery protecting apparatus packaged for preventing overcharging, over discharging, and an overcurrent in a secondary battery, the battery protecting apparatus comprising:
a charging/discharging control chip including a charging control field effect transistor and a discharging control field effect transistor that are connected to the secondary battery;
a protecting chip configured to control, based on a voltage between both ends of the secondary battery, the charging control field effect transistor and the discharging control field effect transistor to prevent the overcharging, the over discharging, and the overcurrent of the secondary battery; and
a lead frame having a connection surface for a plurality of external terminals and having another surface that is in a state of conduction with the connection surface,
wherein said another surface of the lead frame is electrically connected, via a conductive material, to terminals of the charging control field effect transistor and the discharging control field effect transistor formed on a front surface of the charging/discharging control chip,
wherein the protecting chip is mounted such that a back surface of the protecting chip faces a back surface of the charging/discharging control chip via an insulative member,
wherein terminals of the protecting chip are electrically connected to said another surface of the lead frame through bonding wires, and
wherein the charging/discharging control chip and the protecting chip are covered by a resin.

2. The battery protecting apparatus according to claim 1 , wherein a drain of the charging control field effect transistor and a drain of the discharging control field effect transistor are commonly connected in the charging/discharging control chip.

3. The battery protecting apparatus according to claim 2 , wherein a layout of the plurality of external terminals has point symmetry with respect to a central point of an external terminal surface where the plurality of external terminals are exposed at the battery protecting apparatus.

4. The battery protecting apparatus according to claim 1 , wherein the terminals of the protecting chip and the terminals of the charging/discharging control chip are independent from each other.

5. The battery protecting apparatus according to claim 1 ,
wherein among the plurality of external terminals, an external terminal, which is connected to a charging control terminal of the protecting chip, and an external terminal, which is connected to a gate terminal of the charging control field effect transistor, are arranged to be adjacent, and
wherein among the plurality of external terminals, an external terminal, which is connected to a discharging control terminal of the protecting chip, and an external terminal, which is connected to a gate terminal of the discharging control field effect transistor, are arranged to be adjacent.

Assignees

• Tanaka Nobuhito
• Satake Yoshihiro
• Kawaguchi Norihito
• Koshimizu Koji
• Usui Kaoru
• Ohba Yusuke
• Mitsumi Electric Co Ltd

Inventors

• Tanaka Nobuhito
• Satake Yoshihiro
• Kawaguchi Norihito
• Koshimizu Koji
• Usui Kaoru
• Ohba Yusuke

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title