Spin torque MRAM fabrication using negative tone lithography and ion beam etching

Patent metadata

Field	Value
Publication number	US-10170698-B2
Application number	US-201715590545-A
Country	US
Kind code	B2
Filing date	May 9, 2017
Priority date	Aug 31, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A method of forming a pillar includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A layer under the island of photoresist material is etched to establish a pillar defined by the island of photoresist material.

First claim

The invention claimed is:

1. A method for forming a pillar, comprising:
masking a positive tone photoresist material using a dark field reticle and a negative tone developer having a polarity opposite that of the photoresist to provide an island of photoresist material; and
etching a first layer with a first etch under the island of photoresist material to establish a pillar defined by the island of photoresist material.

2. The method of claim 1 , wherein the island of photoresist material is circular.

3. The method of claim 1 , further comprising:
etching a second layer with a second etch to form a second pillar having a diameter about the same as the first pillar; and
etching a stack of layers with a third etch to form a memory stack pillar having a diameter about the same as the second pillar.

4. The method of claim 3 , further comprising etching the first pillar to reduce a diameter of the first pillar before etching the second layer.

5. The method of claim 4 , wherein etching the first pillar reduces the diameter of the first pillar to about 70 nm.

6. The method of claim 3 , further comprising etching the memory stack pillar to reduce a diameter of the memory stack pillar.

7. The method of claim 3 , wherein the island has a diameter of about 150 nm.

8. The method of claim 3 , wherein the stack of layers comprises a magnetic tunnel junction formed from a fixed layer, a tunnel barrier, and a free layer.

9. A method for forming a pillar, comprising:
masking a negative tone photoresist material using a bright field reticle and a positive tone developer having a polarity opposite that of the photoresist to provide an island of photoresist material; and
etching a first layer with a first etch under the island of photoresist material to establish a pillar defined by the island of photoresist material.

10. The method of claim 9 , wherein the developer is n-butyl acetate.

11. The method of claim 9 , wherein the island of photoresist material is circular.

12. The method of claim 9 , further comprising:
etching a second layer with a second etch to form a second pillar having a diameter about the same as the first pillar; and
etching a stack of layers with a third etch to form a memory stack pillar having a diameter about the same as the second pillar.

13. The method of claim 12 , wherein the stack of layers comprises a magnetic tunnel junction formed from a fixed layer, a tunnel barrier, and a free layer.

14. The method of claim 12 , further comprising etching the first pillar to reduce a diameter of the first pillar before etching the second layer.

15. The method of claim 14 , wherein etching the first pillar reduces the diameter of the first pillar to about 70 nm.

16. The method of claim 12 , further comprising etching the memory stack pillar to reduce a diameter of the memory stack pillar.

17. The method of claim 12 , wherein the island has a diameter of about 150 nm.

Assignees

• IBM

Inventors

• Annunziata Anthony J
• Galan Armand A
• Holmes Steve
• Joseph Eric A
• Lauer Gen P
• Lin Qinghuang
• Marchack Nathan P

Classifications

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C2211/5615

  Multilevel magnetic memory cell using non-magnetic non-conducting interlayer, e.g. MTJ · CPC title

• G03F7/70425

  Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning · CPC title

• G03F7/70325

  Resolution enhancement techniques not otherwise provided for, e.g. darkfield imaging, interfering beams, spatial frequency multiplication, nearfield lenses or solid immersion lenses · CPC title

• H01L43/02

  Electricity · mapped topic