Gate-to-bulk substrate isolation in gate-all-around devices

Patent metadata

Field	Value
Publication number	US-10170636-B2
Application number	US-201715603945-A
Country	US
Kind code	B2
Filing date	May 24, 2017
Priority date	Feb 29, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A method for fabricating a semiconductor device comprises forming a sacrificial layer of a first semiconductor material on a substrate, a layer of a second semiconductor material on the sacrificial layer, and a layer of a third semiconductor material on the layer of the second semiconductor material. Portions of the layer of the deposited material are removed to form a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire. An oxidizing process is performed that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin including a first semiconductor material on a substrate, wherein the first semiconductor material includes silicon germanium having a first concentration of germanium in the silicon germanium;
a nanowire over the fin, the nanowire including a second semiconductor material, wherein the second semiconductor material includes silicon germanium having a second concentration of germanium in the silicon germanium; and
wherein the first concentration is at least 10% less than the second concentration;
a first layer of oxide material on exposed portions of the nanowire and a second layer of oxide material on the fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness; and
a gate stack over a channel region of the nanowire, the gate stack including a gate dielectric layer on the nanowire and directly on the second layer of oxide material, a workfunction metal on the gate dielectric layer, and a gate conductor on the workfunction metal.

2. The device of claim 1 further comprising a layer of insulator material on the substrate adjacent to the fin.

3. The device of claim 1 , wherein the second semiconductor material includes Si.

4. The device of claim 1 , wherein the first semiconductor material and the second semiconductor material include dissimilar materials.

5. The device of claim 4 , wherein the dissimilar materials have dissimilar oxidation rates.

6. A semiconductor device comprising:
a fin including a first semiconductor material on a substrate, wherein the first semiconductor material includes silicon germanium having a first concentration of germanium in the silicon germanium; and
a nanowire over the fin, the nanowire including a second semiconductor material, wherein the second semiconductor material includes silicon germanium having a second concentration of germanium in the silicon germanium; and
wherein the first concentration is at least 10% less than the second concentration;
oxide material on the fin; and
a gate stack over a channel region of the nanowire, the gate stack including a gate dielectric layer on the nanowire and directly on the oxide material, a workfunction metal on the gate dielectric layer, and a gate conductor on the workfunction metal.

7. The device of claim 6 , wherein the second semiconductor material includes Si.

8. The device of claim 7 , wherein the workfunction metal is on the gate dielectric layer on the layer of insulator material.

9. The device of claim 6 , wherein the first semiconductor material and the second semiconductor material include dissimilar materials.

10. The device of claim 9 , wherein the dissimilar materials have dissimilar oxidation rates.

11. The device of claim 6 further comprising a layer of insulator material on the substrate adjacent to the fin.

12. The device of claim 6 , wherein the gate dielectric layer is on the layer of insulator material.

13. A semiconductor device comprising:
a substrate;
a fin arranged on the substrate, the fin including a first semiconductor material, wherein the first semiconductor material includes silicon germanium having a first concentration of germanium in the silicon germanium;
a layer of oxide material arranged on the fin;
a nanowire comprising a semiconductor material arranged over the layer of oxide material where the layer of oxide material is disposed between the fin and the nanowire; and
wherein the second semiconductor material includes silicon germanium having a second concentration of germanium in the silicon germanium; and
wherein the first concentration is at least 10% less than the second concentration;
a gate stack arranged around the nanowire and over the layer of oxide material, the gate stack including a gate dielectric layer on the nanowire and directly on the oxide material, a workfunction metal on the gate dielectric layer, and a gate conductor on the workfunction metal.

14. The device of claim 13 , wherein the nanowire includes Si.

15. The device of claim 13 further comprising a layer of insulator material on the substrate adjacent to the fin.

16. The device of claim 13 wherein the fin and the nanowire include dissimilar materials.

17. The device of claim 16 , wherein the dissimilar materials have dissimilar oxidation rates.

Assignees

• IBM

Inventors

• Chang Josephine B
• Guillorn Michael A
• Lauer Isaac
• Miao Xin

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H01L29/42392

  Electricity · mapped topic

• H01L29/78654

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic