Method for forming package structure including intermetallic compound

Patent metadata

Field	Value
Publication number	US-10170429-B2
Application number	US-201715431802-A
Country	US
Kind code	B2
Filing date	Feb 14, 2017
Priority date	Nov 28, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Package structures and methods for forming the same are provided. A package structure includes a package component including a first bump. The package structure also includes an intermetallic compound (IMC) on the first bump. The package structure further includes an integrated circuit die including a second bump on the IMC. The integrated circuit die and the package component are bonded together through the first bump and the second bump. The IMC extends from the first bump to the second bump to provide good physical and electrical connections between the first bump and the second bump.

First claim

What is claimed is:

1. A method for forming a package structure, comprising:
forming a first bump over a substrate;
placing an integrated circuit die comprising a second bump over the substrate, wherein the second bump is placed on the first bump;
reflowing the first bump and the second bump to form a solder joint and bond the integrated circuit die and the substrate together through the solder joint, wherein a first intermetallic compound is formed between the solder joint and the first bump, and a second intermetallic compound is formed between the solder joint and the second bump;
annealing the solder joint, the first bump and the second bump to react the solder joint with the first bump and the second bump until the first intermetallic compound and the second intermetallic compound become connected to each other; and
migrating a remaining portion of the solder joint to the first bump or the second bump during a high-temperature storage test or a temperature cycling test.

2. The method for forming a package structure as claimed in claim 1 , wherein the annealing is performed at a melting point temperature of the solder joint.

3. The method for forming a package structure as claimed in claim 1 , wherein the solder joint is shrunk during the annealing and is substantially eliminated after the annealing.

4. The method for forming a package structure as claimed in claim 1 , further comprising forming an underfill layer surrounding the solder joint, the first bump and the second bump before the annealing.

5. The method for forming a package structure as claimed in claim 1 , further comprising testing the package structure after the first intermetallic compound and the second intermetallic compound become connected to each other.

6. The method for forming a package structure as claimed in claim 1 , further comprising:
forming a conductive feature embedded in the substrate before the formation of the first bump, wherein the conductive feature extends from a first surface of the substrate towards a second surface of the substrate that is opposite to the first surface;
attaching the integrated circuit die to a carrier substrate after the reflowing; and
thinning the substrate from the second surface until the conductive feature is exposed to form a through-substrate via in the substrate, wherein the annealing is performed after the thinning.

7. The method for forming a package structure as claimed in claim 6 , further comprising:
forming a third bump over the second surface of the substrate after the annealing, wherein the third bump is electrically connected to the through-substrate via; and
removing the carrier substrate after the formation of the third bump.

8. The method for forming a package structure as claimed in claim 1 , further comprising:
forming a through-substrate via in the substrate, wherein the through-substrate via is electrically connected to the first bump over a first surface of the substrate;
forming a third bump over a second surface of the substrate that is opposite to the first surface, wherein the third bump is electrically connected to the through-substrate via; and
dicing the substrate to form a sub-package structure, wherein the annealing is performed before the dicing of the substrate.

9. The method for forming a package structure as claimed in claim 8 , further comprising bonding the sub-package structure to a package substrate through the third bump, wherein the annealing is performed over the package substrate before the bonding.

10. A method for forming a package structure, comprising:
forming a first bump over a substrate;
placing a second bump over the first bump, wherein the second bump is formed over an integrated circuit die;
reflowing the first bump and the second bump to bond the integrated circuit die and the substrate together through a solder joint, wherein a first intermetallic compound is formed between the solder joint and the first bump, and a second intermetallic compound is formed between the solder joint and the second bump;
forming a first underfill layer surrounding the solder joint;
annealing the solder joint, the first bump and the second bump, so that a continuous intermetallic compound is formed from the first intermetallic compound and the second intermetallic compound; and
migrating a remaining solder portion of the solder joint to form a vacant region between the continuous intermetallic compound and the first underfill layer.

11. The method for forming a package structure as claimed in claim 10 , wherein a thickness of the continuous intermetallic compound is substantially equal to a distance between the first bump and the second bump.

12. The method for forming a package structure as claimed in claim 10 , wherein the solder joint surrounds the continuous intermetallic compound after the annealing.

13. The method for forming a package structure as claimed in claim 10 , wherein the continuous intermetallic compound is an alloy comprising tin and a metal different from tin.

14. The method for forming a package structure as claimed in claim 10 , further comprising:
forming a through-substrate via in the substrate, wherein the through-substrate via is electrically connected to the first bump over a first surface of the substrate;
forming a third bump over a second surface of the substrate that is opposite to the first surface, wherein the third bump is electrically connected to the through-substrate via;
dicing the substrate to form a sub-package structure; and
reflowing the third bump to bond the sub-package structure and a package substrate together.

15. The method for forming a package structure as claimed in claim 14 , further comprising:
forming a second underfill layer surrounding the third bump after the annealing, and
wherein the first underfill layer surrounds the first bump and the second bump before the annealing.

16. The method for forming a package structure as claimed in claim 14 , further comprising forming a fourth bump on a bottom surface of the package substrate, wherein a size of the first bump is less than that of the fourth bump.

17. A method for forming a package structure, comprising:
forming a first conductive pillar over a substrate and a first solder layer over the first conductive pillar;
forming a second conductive pillar over an integrated circuit die and a second solder layer over the second conductive pillar;
attaching the first solder layer with the second solder layer;
reflowing the first conductive pillar, the second conductive pillar, the first solder layer and the second solder layer to form a first intermetallic compound, a second intermetallic compound, and a solder joint between the first intermetallic compound and the second intermetallic compound;
forming an underfill layer surrounding the solder joint, the first bump and the second bump;
annealing the first conductive pillar, the second conductive pillar, the solder joint, the first intermetallic compound and the second intermetallic compound until the first intermetallic compound and the second intermetallic compound become connected to form a continuous intermetallic compound after the underfill layer is formed, wherein the first solder layer and the second solder layer become a remaining solder portion surrounding the continuous intermetallic compound after the annealing; and
testing the package structure after the continuous intermetallic compound is formed, wherein the remaining solder portion migrates to the first conductive pillar and the second conductive pillar to form a vacant region surro

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Heng-Chi
• Li Chien-Chen
• Li Kuo-Lung
• Cho Cheng-Liang
• Chu Che-Jung
• Liu Kuo-Chio

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title