Implant after through-silicon via (TSV) etch to getter mobile ions

Patent metadata

Field	Value
Publication number	US-10170337-B2
Application number	US-201614994598-A
Country	US
Kind code	B2
Filing date	Jan 13, 2016
Priority date	Jan 13, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.

First claim

What is claimed is:

1. A method of making a semiconductor device, the method comprising:
disposing a mask on a substrate;
etching the mask to form an opening in the mask;
etching a trench in the substrate beneath the opening in the mask;
implanting a dopant, by an implantation technique, in an area of the substrate beneath the opening of the mask such that the dopant extends within the substrate from a substantially vertical sidewall of the trench and substantially horizontal bottom endwall of the trench, the dopant capable of gettering mobile ions that can contaminate the substrate; and
simultaneous with implanting the dopant, implanting a source/drain region of an nFET device adjacent the trench with an element selected from the group consisting of arsenic and phosphorous.

2. The method of claim 1 , further comprising filling the trench with a conductive material to form a through-silicon via (TSV).

3. The method of claim 1 , wherein the dopant comprises arsenic, phosphorus, or a combination thereof.

4. The method of claim 1 , wherein the substrate comprises a base semiconductor substrate, a buried dielectric layer disposed on the base semiconductor substrate, and a silicon layer disposed on the buried dielectric layer.

5. The method of claim 4 , wherein the trench extends about 3 to about 500 microns through the base semiconductor substrate.

6. The method of claim 1 , wherein the dopant getters ions by segregating the ions away from active device areas.

7. The method of claim 1 , wherein the dopant extends through the substrate about 0.25 to about 0.5 microns from the sidewall of the trench.

8. The method of claim 1 , wherein the dopant extends through the substrate about 0.25 to about 0.5 microns from the endwall of the trench.

9. A method of making a semiconductor device, the method comprising:
disposing a mask on a substrate;
etching the mask to form an opening in the mask;
etching a trench in the substrate beneath the opening in the mask;
performing a first implantation technique, after etching the trench, to introduce a dopant in a first area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate;
during the first implantation technique, implanting a source/drain region of an nFET device adjacent the trench with an element selected from the group consisting of arsenic and phosphorous;
performing a second implantation technique, after performing the first implantation technique, to introduce a dopant in a second area of the substrate beneath the opening of the mask, a portion of the second area being different than the first area, and the dopant capable of gettering mobile ions that can contaminate the substrate;
wherein the dopant extends within the substrate from a substantially vertical sidewall of the trench and a substantially horizontal bottom endwall of the trench.

10. The method of claim 9 , wherein the ions are sodium ions or potassium ions.

11. The method of claim 9 , wherein the ions are copper ions.

12. The method of claim 9 , wherein the dopant getters ions by segregating the ions away from active device areas.

13. The method of claim 9 , wherein performing the second implantation technique comprises rotating the substrate to position the substrate at an oblique angle with respect to a normal axis of the substrate during the first implantation technique.

14. The method of claim 13 , further comprising rotating the substrate to position the substrate at another oblique angle and performing a third implantation technique to introduce the dopant in a third area of the substrate, the third area being different than the first or second areas.

Assignees

• IBM

Inventors

• Collins Christopher
• Farooq Mukta G
• Graves-Abe Troy L
• Greene Brian J
• Hannon Robert
• Ho Herbert L
• Kothandaraman Chandrasekharan

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title