Display device

Patent metadata

Field	Value
Publication number	US-10170033-B2
Application number	US-201615358906-A
Country	US
Kind code	B2
Filing date	Nov 22, 2016
Priority date	Nov 24, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.

First claim

What is claimed is:

1. A display device comprising:
a data generator configured to generate a clock-embedded data packet;
a data recoveror configured to receive the clock-embedded data packet to recover data therefrom; and
a controller configured to control operation of the data generator and configured to control operation of the data recoveror,
wherein the data packet comprises a header, a first symbol that includes address information therein, and a second symbol that does not include address information,
wherein the header comprises address information of the first symbol, and
wherein the data recoveror uses address information in the header to recover data of the first symbol.

2. The display device of claim 1 , wherein the first symbol comprises
address bits indicative of address information of a subsequent first symbol, and
a data bit indicative of data associated with the subsequent first symbol.

3. The display device of claim 2 , wherein a first symbol that is a last first symbol comprises
a predetermined data bit, and
predetermined address bits indicative of the last first symbol.

4. The display device of claim 1 , wherein the data packet comprises 2 (n−1) −2 symbols, and
each of the symbols comprises n-bit data, wherein n is a natural number that is greater than or equal to 3.

5. The display device of claim 1 , wherein the data generator comprises:
a data processor configured to receive image data and to embed a clock signal therein; and
a data transformer configured to transform at least a part of the image data into the first symbol to generate the data packet.

6. The display device of claim 5 , wherein the data transformer is configured to transform a symbol whose bits all have a same value into the first symbol.

7. The display device of claim 1 , wherein the address information of the first symbol comprises an absolute address of a subsequent first symbol.

8. The display device of claim 5 , wherein data generator further comprises a counter configured to count a distance between successive first symbols,
wherein the address information of the first symbol comprises the distance between the first symbol and the subsequent first symbol.

9. The display device of claim 1 , wherein the address information of the header comprises an absolute address of the first symbol.

10. A display device comprising:
a data recoveror configured to receive a clock-embedded data packet to recover data therefrom; and
a controller configured to control operation of the data recoveror,
wherein the data packet comprises, a first symbol that includes address information therein, a second symbol that does not include address information, and a header that includes address information of the first symbol, wherein the first symbol comprises a data bit and address bits indicative of address information of a subsequent first symbol, and the header comprises address bits of the first symbol, and
wherein the data recoveror uses the address information in the header to recover data of the first symbol.

11. The display device of claim 10 , wherein the data recoveror comprises a clock recoveror configured to recover a clock signal from the clock-embedded data packet.

12. The display device of claim 11 , wherein the data recoveror further comprises a counter configured to count a distance between successive first symbols,
wherein the address information of the first symbol comprises the distance between the first symbol and the subsequent first symbol.

13. The display device of claim 10 ,
wherein the data recoveror is configured to recover the address bits of a subsequent first symbol as data bits if the address bits of subsequent first symbol are less than the address bits of the first symbol, and
the data recoveror is configured to recover the address bits of the subsequent first symbol if an address of the subsequent first symbol is equal to the address bits of the first symbol.

14. The display device of claim 10 , wherein the data recoveror is configured to recover data of the subsequent first symbol from the data bits of the first symbol.

15. A display device comprising:
a data generator configured to generate a clock-embedded data packet; and
a data recoveror configured to receive the clock-embedded data packet to recover data therefrom,
wherein the data packet comprises a first symbol that includes address information therein, a second symbol that does not include address information, and a header that includes address information of the first symbol,
wherein the data packet comprises 2 (n−1) −2 symbols, and
each of the symbols comprises n-bit data, wherein n is a natural number that is greater than or equal to 3.

16. The display device of claim 15 , wherein the first symbol comprises
address bits indicative of address information of a subsequent first symbol, and
a data bit indicative of data associated with the subsequent first symbol, wherein
the data generator transforms a symbol whose bits all have a same value into the first symbol.

17. The display device of claim 16 , wherein the data recoveror is configured to recover the address bits of the subsequent first symbol if an address of the subsequent first symbol is equal to the address bits of the first symbol, and to recover data of the subsequent first symbol from the data bits of the first symbol, and
the data recoveror is configured to recover the address bits of a subsequent first symbol as data bits if the address bits of subsequent first symbol are less than the address bits of the first symbol.

18. The display device of claim 16 , further comprising:
a recoveror controller configured to control operation of the data recoveror;
a generator controller configured to control operation of the data generator; and
a clock recoveror configured to recover a clock signal from the clock-embedded data packet.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Kwi Sung
• Baek Dong Hoon
• Lee Dong Myung
• Lim Hyun Wook
• Jin Eun Young
• Lee Jae Youl

Classifications

• G09G2310/0221

  with use of split matrices (G09G3/3644 and G09G3/3666 take precedence) · CPC title

• G09G3/2096 Primary

  Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167) · CPC title

• G09G3/2092

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

• G09G2370/08

  Details of image data interface between the display device controller and the data line driver circuit · CPC title

• G09G2370/10

  Use of a protocol of communication by packets in interfaces along the display data pipeline · CPC title