Multi-topology logic gates

Patent metadata

Field	Value
Publication number	US-10169617-B2
Application number	US-201515301409-A
Country	US
Kind code	B2
Filing date	Apr 29, 2015
Priority date	Apr 29, 2014
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

An RMTL gate includes at least two logic blocks, where at least one of the logic blocks operates in multiple modes. The respective logic block mode(s) are selected by a topology selector which applies mode control signals to the logic blocks in order to obtain a selected topology for logic circuit operation. RMTL logic gates may be cascaded and/or interconnected to form an RMTL logic circuit with multiple logic gates which may operate with dynamically varying topologies. Use of random, semi-random or specified control sequences may protect the logic circuit against security attacks.

First claim

What is claimed is:

1. A multi-topology logic gate for performing a specified logic function, said logic gate comprising logic inputs and a logic output, comprising:
a logic output connection configured to output a logic output signal;
a plurality of logic input connections configured to input logic signals;
at least two logic blocks associated with said logic input connections and said logic output connection, each of said blocks respectively comprising a plurality of logic inputs connectable to said logic input connections and a logic output connected to said logic output connection, wherein at least one of said logic blocks is configured to operate in a plurality of modes in accordance with a respective mode control signal; and
a topology selector associated with said at least two logic blocks, configured to apply mode control signals to said logic blocks so as to operate said logic gate in a plurality of topologies.

2. A multi-topology logic gate according to claim 1 , wherein said logic blocks comprise respective transistor networks.

3. A multi-topology logic gate according to claim 1 , wherein said logic blocks implement a same logic function in different respective topologies.

4. A multi-topology logic gate according to claim 1 , wherein logic blocks having a plurality of modes of operation are respectively configured to operate in at least two of static, dynamic and on-off modes, in accordance with said mode control signals.

5. A multi-topology logic gate according to claim 1 , wherein at least two of said logic blocks are configured to operate in a plurality of modes in accordance with a respective mode control signal.

6. A multi-topology logic gate according to claim 1 , further comprising a logic block with a single mode of operation.

7. A multi-topology logic gate according to claim 1 , wherein at least one of said mode control signals is a constant voltage.

8. A multi-topology logic gate according to claim 1 , wherein at least one of said mode control signals is a clock signal.

9. A multi-topology logic gate according to claim 1 , wherein said topology selector is configured to connect a pre-charge clock signal to said logic output connection during pull-down dynamic logic operation.

10. A multi-topology logic gate according to claim 1 , wherein said topology selector is configured to connect a pre-discharge clock signal to said logic output connection during pull-up dynamic logic operation.

11. A multi-topology logic gate according to claim 1 , wherein said topology selector is configured to switch said logic gate between said topologies randomly.

12. A multi-topology logic gate according to claim 1 , wherein said topology selector is configured to switch said logic gate between said topologies in accordance with a specified sequence.

13. A multi-topology logic gate according to claim 1 , wherein said topology selector comprises topology control inputs and is configured to switch said logic gate between said topologies in accordance with external signals input to said topology control inputs.

14. A multi-topology logic gate according to claim 1 , wherein said topology selector is configured to direct logic input signals to respective logic inputs of selected ones of said logic blocks, in accordance with a current topology.

15. A multi-topology logic gate according to claim 1 , wherein logic inputs of at least one of said logic blocks are fixedly connected to said logic input connections.

Assignees

• Univ Bar Ilan

Inventors

• Fish Alexander
• Avital Moshe
• Dagan Hadar
• Keren Osnat

Classifications

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F2221/034

  Test or assess a computer or a system · CPC title

• H03K19/17768

  for security · CPC title

• G06F21/755 Primary

  with measures against power attack · CPC title