Variation-aware circuit simulation

Patent metadata

Field	Value
Publication number	US-10169507-B2
Application number	US-201715439794-A
Country	US
Kind code	B2
Filing date	Feb 22, 2017
Priority date	Nov 29, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.

First claim

What is claimed is:

1. An integration circuit (IC) simulation method, comprising:
(a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit;
(b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters;
(c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavior model; and
(d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation, wherein the first variation comprises at least one first local mismatch variation, wherein the at least one first local mismatch variation corresponds to a variation of a design parameter of an element of the first sub-circuit.

2. The IC simulation method of claim 1 , wherein the first variation further comprises a process-voltage-temperature corner.

3. The IC simulation method of claim 1 , wherein the step (d) comprises performing a transistor-level simulation on the first sub-circuit with the use of the first variation.

4. The IC simulation method of claim 1 , further comprising (e) using the first behavior model and the one or more behavior-level parameters of the first behavior model that incorporates the first variation to provide a behavior output.

5. The IC simulation method of claim 1 , wherein the system-level circuit comprises a second sub-circuit.

6. The IC simulation method of claim 5 , wherein the step (b) further comprises:
providing a second behavior model that is determined based on an operation of the second sub-circuit, wherein the second behavior model is a function of one or more respective behavior-level parameters.

7. The IC simulation method of claim 6 , wherein the step (c) further comprises:
providing a second variation, wherein the second variation comprises at least one second local mismatch variation, wherein the at least one second local mismatch variation corresponds to a variation of a design parameter of an element of the second sub-circuit.

8. The IC simulation method of claim 7 , wherein the second variation is different from the first variation.

9. The IC simulation method of claim 7 , wherein the second variation is identical to the first variation.

10. The IC simulation method of claim 7 , wherein the step (c) further comprises:
incorporating the second variation into each of the one or more behavior-level parameters of the second behavior model.

11. The IC simulation method of claim 10 , wherein the step (d) comprises:
simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation and the one or more behavior-level parameters of the second behavior model that incorporates the second variation, respectively.

12. The IC simulation method of claim 11 , wherein the step (d) further comprises:
using the second behavior model and the one or more behavior-level parameters of the second behavior model that incorporates the second variation to provide a behavior output;
providing the behavior output to the first behavior model as a behavior input so as to simulate the first sub-circuit by using the behavioral input, the first behavior model, and the one or more behavior-level parameters that incorporates the first variation.

13. A system comprising:
a non-transitory memory configured to store a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; and
one or more hardware processors in communication with the non-transitory memory and configured to:
(a) receive the design netlist;
(b) receive a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters;
(c) incorporate a first variation into each of the one or more behavior-level parameters of the first behavior model; and
(d) simulate the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation, wherein the first variation comprises at least one first local mismatch variation, wherein the at least one first local mismatch variation corresponds to a variation of a design parameter of an element of the first sub-circuit.

14. The system of claim 13 , wherein the first variation further comprises at least one of process-voltage-temperature corners.

15. The system of claim 13 , wherein, at the step (c), the one or more hardware processors are further configured to perform a transistor-level simulation on the first sub-circuit with the use of the first variation.

16. The system of claim 13 , wherein, at the step (d), the one or more hardware processors are further configured to use the first behavior model and the one or more behavior-level parameters of the first behavior model that incorporates the first variation to provide a behavioral output.

17. A system comprising:
a non-transitory memory configured to store a design netlist of a system-level circuit, wherein the system-level circuit comprises first and second sub-circuits; and
one or more hardware processors in communication with the non-transitory memory and configured to:
(a) receive the design netlist;
(b) receive a first behavior model that is determined based on an operation of the first sub-circuit and a second behavior model that is determined based on an operation of the second sub-circuit, wherein the first behavior model is a function of a first plurality of behavior-level parameters and the second behavior model is a function of a second plurality of behavior-level parameters;
(c) incorporate a first variation into each of the first and second pluralities of behavior-level parameters; and
(d) simulate the system-level circuit based on the first and second pluralities of behavior-level parameters, wherein the first variation comprises at least one first local mismatch variation, wherein the at least one first local mismatch variation corresponds to a variation of a design parameter of an element of the first sub-circuit and the second-sub-circuit.

18. The system of claim 17 , wherein the first variation further comprises at least one of process-voltage-temperature corners.

19. The system of claim 17 , wherein, at the step (c), the one or more hardware processors are further configured to:
receive a second variation that is different from the first variation, wherein the second variation comprises at least one second local mismatch variation, wherein the at least one second local mismatch variation corresponds to a variation of a design parameter of an element of the second sub-circuit.

20. The system of claim 19 , at the step (c), the one or more hardware processors are further configured to:
incorporate the first and second variation into each of the first and second pluralities of behavior-level parameters, respectively.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Chin-Cheng
• Hu Wei-Yi

Classifications

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F17/5022

  Physics · mapped topic

• G06F17/5036 Primary

  Physics · mapped topic