Timing context generation with multi-instance blocks for hierarchical analysis

Patent metadata

Field	Value
Publication number	US-10169501-B1
Application number	US-201615182353-A
Country	US
Kind code	B1
Filing date	Jun 14, 2016
Priority date	Jun 14, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

First claim

What is claimed is:

1. A method for hierarchical timing comprising:
accessing a memory of a computing device to obtain a first circuit design, the first circuit design comprising a plurality of instances of a first block;
determining, by one or more hardware processors of the computing device, a plurality of multi-mode multi-corner (MMMC) views for the first circuit design;
generating, by the one or more hardware processors, a plurality of timing contexts for the circuit design, each timing context of the plurality of timing contexts being generated from a different combination of an instance of the plurality of instances and an MMMC view of the plurality of MMMC views;
generating, by the one or more hardware processors, an analysis view output file comprising a plurality of content MMMC views, the plurality of content MMMC views comprising the plurality of MMMC views and the plurality of timing contexts;
determining a block timing merge threshold for the circuit design;
determining a first phase value for a first propagation point within the circuit design using a first timing context and a first MMMC view from the analysis view output file;
determining a second phase value for the first propagation point within the circuit design using a second timing context and a second MMMC view from the analysis view output file;
generating a merged phase value by comparing the block timing merge threshold with a difference between the first phase value and the second phase value; and
fabricating semiconductor devices using the circuit design with the hierarchical timing.

2. The method of claim 1 , further comprising:
performing a timing analysis with the analysis view output file using each timing context of the plurality of timing contexts; and
generating a plurality of timing reports from the timing analysis using each timing context of the plurality of timing contexts.

3. The method of claim 1 , wherein the plurality of timing contexts comprises input and output boundary condition information for one or more circuit elements of the multi-instance block.

4. The method of claim 3 , wherein the input and output boundary condition information is based on one or more of:
clock arrival times, phase tags representing upstream path constraints, driver information, data required times, downstream path constraints, external parasitics, and external timing window aggressors.

5. The method of claim 1 , further comprising:
determining, by the computing device, a plurality of propagation points associated with the first block of the circuit design, wherein the plurality of propagation points comprises the first propagation point;
calculating, by the computing device for a first instance of the first block, a first set of phase values, wherein the first set of phase values comprises a first corresponding phase value for each propagation point of the plurality of propagation points, and wherein the first set of phase values are based on a first timing context for the first instance of the plurality of timing contexts;
calculating, by the computing device for a second instance of the first block, a second set of phase values comprising second corresponding phase values for each propagation point of the plurality of propagation points, wherein the second set of phase values are based on a second timing context for the second instance of the plurality of timing contexts;
generating a corresponding merged phase value for each point of the plurality of propagation points by comparing the block timing merge threshold with each difference between the first corresponding phase value and the second corresponding phase value for each propagation point; and
calculating a required time for each propagation point of the plurality of propagation points using the corresponding merged phase value for each point; and
storing the first set of phase values and the second set of phase values as timing analysis data in a memory of the computing device.

6. The method of claim 5 , wherein the first propagation point of the plurality of propagation points is associated with an input for a first circuit element of the first block; and
wherein a second propagation point of the plurality of propagation points is associated with an output for the first circuit element of the first block.

7. The method of claim 5 , further comprising:
calculating a first slack value for the first instance using the merged phase value; and
calculating a second slack value for the second instance using the merged phase value;
wherein generating the merged phase value further comprises selecting a later delay value from the first phase value and the second phase value.

8. The method of claim 1 , further comprising:
determining, by the computing device, a plurality of propagation points associated with each block of the circuit design;
calculating, by the computing device for each instance of each block, a corresponding set of phase values based on each timing context for each instance;
for each block, merging phase values for each propagation point from each instance using a greatest delay for each propagation point to generated merged phase values; and
determining a single set of delays for each block using the merged phase values for the associated block.

9. The method of claim 8 , further comprising:
receiving a user input selecting between a full accuracy timing analysis mode and an estimate timing analysis mode;
performing a first timing analysis using the set of phase values based on each timing context for each instance in the full accuracy timing analysis mode; and
performing a second timing analysis using the merged phase values in the estimate timing analysis mode.

10. The method of claim 1 , further comprising:
analyzing the plurality of timing contexts to identify compatible timing contexts for a first instance of the first block; and
merging the compatible timing contexts to generate a merged timing context for the first instance of the first block.

11. A system for hierarchical timing analysis of a circuit design comprising a multi-instance block, the system comprising:
one or more processors configured to execute instructions to perform operations in analyzing the integrated circuit design; and
a non-transitory processor readable medium to store the instructions that when executed, cause the one or more processors to perform operations comprising:
accessing a first circuit design, the first circuit design comprising a plurality of instances of a first block;
determining a plurality of multi-mode multi-corner (MMMC) views for the first circuit design;
generating a plurality of timing contexts for the circuit design, each timing context of the plurality of timing contexts being generated from a different combination of an instance of the plurality of instances and an MMMC view of the plurality of MMMC views; and
generating an output file comprising a plurality of content MMMC views, the plurality of content MMMC views comprising the plurality of MMMC views and the plurality of timing contexts for each instance of the circuit design;
determining a block timing merge threshold for the integrated circuit design;
determining a first phase value for a first propagation point within the integrated circuit design using a first timing context and a first MMMC view from the output file;
determining a second phase value for the first propagation point within the integrated circuit design using a second timing context and a second MMMC view from the output file;
generate a merged phase value by comparing the block timing merge threshold with a difference between the first phase value of the first set of phase

Assignees

• Cadence Design Systems Inc

Inventors

• Kulshreshtha Pawan
• Dhuria Amit

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F17/5031 Primary

  Physics · mapped topic