Techniques for handling interrupt related information in a data processing system

Patent metadata

Field	Value
Publication number	US-10169270-B2
Application number	US-201615340083-A
Country	US
Kind code	B2
Filing date	Nov 1, 2016
Priority date	Nov 16, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A technique for handling queued interrupts includes determining, by an interrupt presentation controller (IPC), whether a received memory mapped input/output (MMIO) store is associated with preempting a virtual processor (VP) thread. In response to determining the MIMO store is associated with preempting the VP thread, the IPC writes interrupt context information of the VP thread to a specified location in memory.

First claim

What is claimed is:

1. A method of handling queued interrupts, comprising:
determining, by an interrupt presentation controller (IPC), whether a received memory mapped input/output (MMIO) store request is associated with preempting a virtual processor (VP) thread;
in response to determining the MMIO store request is associated with preempting the VP thread:
writing, by the IPC, interrupt context information of the VP thread to a specified location in memory;
determining, by the IPC, whether an interrupt context table (ICT) indicates an interrupt is currently pending for the VP thread; and
in response to determining the ICT indicates an interrupt is currently pending for the VP thread, issuing, by the IPC, a redistribute message for the interrupt that is currently pending that causes the interrupt to be reassigned to a different VP thread.

2. The method of claim 1 , wherein the MMIO store request causes the IPC to reset a valid bit in a row of the interrupt context table (ICT) associated with the VP thread.

3. The method of claim 2 , wherein the specified location in memory is sourced from a reporting address field of the row in the ICT.

4. The method of claim 1 , wherein the writing is performed via direct memory access (DMA) transfer.

5. The method of claim 2 , wherein the ICT is located in main memory.

6. A processing unit for a multithreaded data processing system, the processing unit comprising:
a processor core; and
an interrupt presentation controller (IPC) coupled to the processor core, wherein the IPC is configured to:
determine whether a memory mapped input/output (MMIO) store request received from the processor core is associated with preempting a virtual processor (VP) thread;
in response to determining the received MMIO store request is associated with preempting the VP thread:
write interrupt context information of the VP thread to a specified location in memory;
determine whether an interrupt context table (ICT) indicates an interrupt is currently pending for the VP thread; and
in response to determining the ICT indicates an interrupt is currently pending for the VP thread, issue a redistribute message for the interrupt that is currently pending that causes the interrupt to be reassigned to a different VP thread.

7. The processing unit of claim 6 , wherein the MMIO store request causes the IPC to reset a valid bit in a row of the interrupt context table (ICT) associated with the VP thread.

8. The processing unit of claim 7 , wherein the specified location in memory is sourced from a reporting address field of the row in the ICT.

9. The processing unit of claim 6 , wherein the writing is performed via direct memory access (DMA) transfer.

10. The processing unit of claim 7 , wherein the ICT is located in main memory.

11. A design structure tangibly embodied in a computer-readable storage device for designing, manufacturing, or testing an integrated circuit, wherein the design structure comprises:
a processor core; and
an interrupt presentation controller (IPC) coupled to the processor core, wherein the IPC is configured to:
determine whether a memory mapped input/output (MMIO) store request received from the processor core is associated with preempting a virtual processor (VP) thread;
in response to determining the received MMIO MIMO store request is associated with preempting the VP thread:
write interrupt context information of the VP thread to a specified location in memory;
determine whether an interrupt context table (ICT) indicates an interrupt is currently pending for the VP thread; and
in response to determining the ICT indicates an interrupt is currently pending for the VP thread, issue a redistribute message for the interrupt that is currently pending that causes the interrupt to be reassigned to a different VP thread.

12. The design structure of claim 11 , wherein the MMIO store request causes the IPC to reset a valid bit in a row of the interrupt context table (ICT) associated with the VP thread.

13. The design structure of claim 12 , wherein the specified location in memory is sourced from a reporting address field of the row in the ICT.

14. The design structure of claim 11 , wherein the writing is performed via direct memory access (DMA) transfer and the ICT is located in main memory.

Assignees

• IBM

Inventors

• Arndt Richard L
• Auernhammer Florian A

Classifications

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title

• G06F2212/70

  Details relating to dynamic memory management · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F12/122

  of the least frequently used [LFU] type, e.g. with individual count value · CPC title