Module based data transfer

Patent metadata

Field	Value
Publication number	US-10169257-B2
Application number	US-201615048690-A
Country	US
Kind code	B2
Filing date	Feb 19, 2016
Priority date	Mar 6, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A method and system for direct memory transfers between memory modules are described that includes sending a request to a first memory module and storing the data sent on a memory bus by the first memory module into a second memory module. The direct transfer of data between the first and second memory modules reduces power consumption and increases performance.

First claim

What is claimed is:

1. A method for transferring data between memory modules, the method comprising:
sending a read request to a first memory module, the first memory module comprising one or more non-volatile memory devices;
sending a write request to a second memory module, the second memory module comprising one or more volatile memory devices, wherein the write request comprises an indicator that the second memory module is to capture data from a data bus, the data sent directly from the first memory module;
in response to the read request, sending data from the first memory module on the data bus, wherein the data bus electrically couples the first memory module, the second memory module, and a processor; and
in response to the write request, storing the data from the data bus into the second memory module.

2. The method of claim 1 , wherein the first memory module and the second memory modules are dual in-line memory modules (DIMMs) and the data is transferred directly from the first memory module to the second memory module via the data bus, wherein the first memory module and the second memory module share the data bus.

3. The method of claim 1 , wherein the data stored into the second memory module is received directly from the first memory module via the data bus.

4. The method of claim 1 further comprising:
accessing the data via the data bus using a buffer; and performing error checking on the data using the buffer.

5. The method of claim 4 further comprising:
in response to determining an error based on the error checking, sending an error indicator to the second memory module.

6. The method of claim 1 further comprising:
performing an initialization process for a direct transfer of data from the first memory module to the second memory module.

7. A system comprising:
a processor;
a first memory module comprising one or more non-volatile memory devices;
a second memory module comprising one or more volatile memory devices; and
a memory bus coupling the processor, the first memory module, and the second memory module, wherein the processor is configured to initiate a copy operation of data of the first memory module directly to the second memory module by sending a read request to the first memory module and a write request to the second memory module, wherein the write request comprises an indicator that the second memory module is to capture data from the memory bus, the data sent directly from the first memory module; and wherein the first memory module is configured to send data on the memory bus in response to the read request, and wherein the second memory module is configured to store the data from the memory bus into the second memory module.

8. The system of claim 7 , wherein the first memory module and the second memory modules are dual in-line memory modules (DIMMs) and the data is transferred directly from the first memory module to the second memory module via the memory bus, wherein the first memory module and the second memory module share the memory bus.

9. The system of claim 7 further comprising:
a buffer configured to transmit a data signal and a data strobe signal with different phase alignments.

10. The system of claim 7 further comprising a system board comprising the buffer.

11. The system of claim 7 further comprising:
a buffer configured to receive a data signal and a data strobe signal having a same phase alignment and further configured to transmit the data signal and the data strobe signal with a different phase alignment.

12. The system of claim 11 , wherein the second memory module comprises the buffer.

13. The system of claim 11 , wherein the first memory module comprises the buffer.

14. The system of claim 7 , wherein the processor is configured to perform an error check operation on the data on the memory bus and in response to determining an error therefrom, the processor is further configured to contemporaneously signal the second memory module to cancel the write request.

15. The system of claim 7 , wherein the processor is configured to perform an initialization process for a direct transfer of data from the first memory module to the second memory module.

16. A method for copying data, the method comprising:
receiving a copy request to copy data, wherein the copy request comprises a source address and a destination address;
determining whether a first memory module associated with the source address and a second memory module associated with the destination address are coupled to a memory bus;
in response to determining the first memory module and the second memory module are coupled to the memory bus, sending a read request to a first memory module, the first memory module comprising one or more non-volatile memory devices, wherein the first memory module is configured to send data associated with the source address over the memory bus; and
sending a write request to the second memory module, wherein the write request comprises an indicator that the second memory module is to capture data from the memory bus, the data sent directly from the first memory module, and the second memory module comprising one or more volatile memory devices, wherein in response to the write request the second memory module accesses the data from the memory bus.

17. The method of claim 16 , wherein the first memory module and the second memory modules are dual in-line memory modules (DIMMs) and the data is transferred directly from the first memory module to the second memory module via the memory bus, wherein the first memory module and the second memory module share the memory bus.

18. The method of claim 16 further comprising:
sending a signal to a processor to perform an error checking process on the data on the memory bus.

19. The method of claim 18 further comprising:
in response to the processor determining an error as a result of the error checking process, receiving an error signal from the processor.

20. The method of claim 16 , wherein the first memory module comprises non-volatile memory.

Assignees

• Rambus Inc

Inventors

• Woo Steven
• Secker David

Classifications

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G06F13/1673 Primary

  using buffers · CPC title

• G06F11/00

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title

• G06F3/0632

  by initialisation or re-initialisation of storage systems · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title