Heterogeneous package in DIMM

Patent metadata

Field	Value
Publication number	US-10169242-B2
Application number	US-201615294387-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Oct 16, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

First claim

What is claimed is:

1. A memory system comprising:
a memory module including:
a first memory device including a first memory and a first memory controller controlling the first memory to store data; and
a second memory device including a second memory and a second memory controller controlling the second memory to store data; and
a processor executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices,
wherein the first and second memories are separated from the processor,
wherein the processor accesses the second memory device through the first memory device,
wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal,
wherein the memory module includes one or more memory stacks,
wherein one or more volatile memories as the first memory, one or more non-volatile memories as the second memory, and the first and second memory controllers are stacked in the memory stacks,
wherein the first and second memory devices stacked in the memory stacks are communicatively coupled to each other through a through-via,
wherein the first and second memory controllers interface with the first and second memories and the processor through the through-via.

2. The memory system of claim 1 ,
wherein the first and second memories have first and second latencies, respectively,
wherein the first and second memory devices maintain information of the first and second latencies, respectively, and
wherein the processor separately communicates with each of the first and second memories according to the information of the first and second latencies provided from the first and the second memory devices.

3. The memory system of claim 1 , wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

4. The memory system of claim 1 , wherein the value of the memory selection field indicates two or more among the processor and the first and second memory devices as a source and a destination of the signal.

5. The memory system of claim 1 , wherein the value of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

6. The memory system of claim 1 , wherein the second memory device is a non-volatile random access memory device.

7. The memory system of claim 1 ,
wherein the first and second memories form a single package, and the single package is mounted on a dual in-line memory module.

8. A memory system comprising:
a memory module including:
a first memory device including a first memory and a first memory controller controlling the first memory to store data; and
a second memory device including a second memory and a second memory controller controlling the second memory to store data; and
a processor executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices,
wherein the first and second memories are separated from the processor,
wherein the processor accesses the second memory device through the first memory device,
wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal,
wherein the first memory includes a high-capacity memory, which has a lower latency than the second memory and operates as a cache memory for the second memory, and a high-speed memory, which has a lower latency than the high-capacity memory and operates as a cache memory for the high-capacity memory,
wherein the first memory controller includes a high-capacity memory cache controller controlling the high-capacity memory to store data, and a high-speed memory cache controller controlling the high-speed memory to store data,
wherein the first memory device is implemented in a memory module,
wherein the memory module includes one or more high-speed memories and one or more high-capacity memories, and
wherein the high-capacity memories has a stack structure, in which one or more volatile memories are stacked.

9. The memory system of claim 8 ,
wherein the memory module further includes the second memory device, and
wherein the memory module including the high-speed operation memory and the high-capacity memory further includes the second memory.

10. The memory system of claim 9 ,
wherein the high-speed, high-capacity and second memories have high-speed, high-capacity and second latencies, respectively,
wherein the first memory device maintains information of the high-speed and high-capacity latencies and the second memory device maintains the information of the second latency respectively, and
wherein the processor separately communicates with each of the high-speed, high-capacity and second memories according to the information of the high-speed, high-capacity and second latencies provided from the first and second memory devices.

11. The memory system of claim 9 , wherein the value of the memory selection field indicates one of the first and second memory devices as a destination of the signal.

12. The memory system of claim 9 , wherein the value of the memory selection field indicates two or more among the processor and the first and second memory devices as a source and a destination of the signal.

13. The memory system of claim 9 , wherein the value of the handshaking information field indicates the signal as one of a data request signal from the processor to the second memory, a data ready signal from the second memory to the processor and a session start signal from the processor to the second memory.

14. The memory system of claim 9 , wherein the second memory device is a non-volatile random access memory device.

15. The memory system of claim 8 ,
wherein the first and second memories form a single package, and the single package is mounted on a dual in-line memory module.

16. A memory system comprising:
a memory module including:
a first memory device including a first memory and a first memory controller controlling the first memory to store data; and
a second memory device including a second memory and a second memory controller controlling the second memory to store data; and
a processor accessing the first memory, and accessing the second memory through the first memory device,
wherein the first memory controller transfers a signal between the processor and the second memory device based on at least one of values of a memory selection field and a handshaking information field included in the signal,
wherein the memory module includes one or more memory stacks,
wherein one or more volatile memories as the first memory and the first memory controller are stacked in the memory stacks,
wherein the first and second memory devices stacked in the memory stacks are communicatively coupled to each other through a through-via, and
wherein the first and second memory controllers interface with the first and second memories and the processor through the through-via.

17. The memory system of claim 16 ,
wherein the volatile memories include one or more high-capacity memories, each of which has a lower latency than the second memory and operates as a ca

Assignees

• Sk Hynix Inc

Inventors

• Lee Yong-Woo
• Kim Min-Chang
• Kim Chang-Hyun
• Lee Do-Yun
• Lee Jae-Jin
• Jung Hun-Sam

Classifications

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F12/0868 Primary

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• G06F2212/451

  Stack data · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title