Hardware for parallel command list generation

US10169072B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10169072-B2
Application numberUS-85316110-A
CountryUS
Kind codeB2
Filing dateAug 9, 2010
Priority dateSep 23, 2009
Publication dateJan 1, 2019
Grant dateJan 1, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for providing an initial default state for a multi-threaded processing environment, the method comprising: receiving, from an application program, a plurality of separate command lists corresponding to a plurality of parallel threads associated with the application program, wherein each thread in the plurality of parallel threads generates a separate command list in the plurality of command lists; causing a first command list associated with a first thread included in the plurality of parallel threads to be executed by a processing unit based on a first processing state, wherein the first processing state includes a set of graphics parameters; after the processing unit executes the first command list, causing a second command list associated with a second thread included in the plurality of parallel threads to be executed by the processing unit based on the first processing state inherited from the first command list; causing a single unbind method to be executed by the processing unit, wherein the unbind method resets one or more parameters included in the set of graphics parameters to an initial processing state; and causing commands included in a third command list to be executed by the processing unit after the unbind method is executed. 2. The method of claim 1 , wherein the processing unit comprises a graphics processing unit. 3. The method of claim 1 , wherein the processing unit comprises a core of a central processing unit. 4. The method of claim 1 , wherein the unbind method is sequentially the first command in the second command list to be executed by the processing unit. 5. The method of claim 1 , wherein one or more rows of a memory unit are configured to store the first processing state, and further comprising setting one or more bits associated with each of the one or more rows to an invalid state. 6. The method of claim 1 , wherein resetting the one or more parameters included in the set of graphics parameters comprises clearing one or more cache lines in a cache memory associated with the first processing state. 7. The method of claim 1 , wherein resetting the one or more parameters included in the set of graphics parameters comprises clearing one or more banks of a banked memory associated with the first processing state. 8. The method of claim 1 , wherein causing the commands included in the second command list to be executed comprises executing the commands based on the one or more parameters that have been reset to the initial processing state. 9. The method of claim 1 , wherein the commands included in the first command list comprise at least one draw method to be executed by one or more stages in a graphics processing pipeline. 10. The method of claim 1 , further comprising, before the unbind method is executed: causing commands included in a first command list associated with the second thread of the plurality of parallel threads to be executed by the processing unit; and switching from executing commands included in the first command list associated with the second thread to executing commands included in the third command list. 11. The method of claim 1 , wherein each of the different command lists is associated with a different driver, and each different driver corresponds to a different thread in the plurality of parallel threads. 12. The method of claim 1 , further comprising the steps of propagating the processing state from one command list in the different command lists to another command list in the different command lists in order to implement state inheritance across the different command lists. 13. The method of claim 1 , further comprising receiving an indication from the application program that the first command list is to be executed by the processing unit. 14. A non-transitory computer-readable storage medium storing instructions that, when executed, cause a computer system to provide an initial default state for a multi-threaded processing environment, by performing the steps of: receiving, from an application program, a plurality of separate command lists corresponding to a plurality of parallel threads associated with the application program, wherein each thread in the plurality of parallel threads generates a separate command list in the plurality of command lists; causing a first command list associated with a first thread included in the plurality of parallel threads to be executed by a processing unit based on a first processing state, wherein the first processing state includes a set of graphics parameters; after the processing unit executes the first command list, causing a second command list associated with a second thread included in the plurality of parallel threads to be executed by the processing unit based on the first processing state inherited from the first command list; causing a single unbind method to be executed by the processing unit, wherein the unbind method resets one or more parameters included in the set of graphics parameters to an initial processing state; and causing commands included in a third command list to be executed by the processing unit after the unbind method is executed. 15. The computer-readable storage medium of claim 14 , wherein the processing unit comprises a graphics processing unit. 16. The computer-readable storage medium of claim 14 , wherein the processing unit comprises a core of a central processing unit. 17. The computer-readable storage medium of claim 14 , wherein the unbind method is sequentially the first command in the second command list to be executed by the processing unit. 18. The computer-readable storage medium of claim 14 , wherein one or more rows of a memory unit are configured to store the first processing state, and further comprising setting one or more bits associated with each of the one or more rows to an invalid state. 19. The computer-readable storage medium of claim 14 , wherein resetting the one or more parameters included in the set of graphics parameters comprises clearing one or more cache lines in a cache memory associated with the first processing state. 20. The computer-readable storage medium of claim 14 , wherein resetting the one or more parameters included in the set of graphics parameters state comprises clearing one or more banks of a banked memory associated with the first processing state. 21. A computer system, comprising: a processor; and a memory storing instructions that, when executed by the processor, cause the processor to provide an initial default state for a multi-threaded processing environment by performing the steps of: receiving, from an application program, a plurality of separate command lists corresponding to a plurality of parallel threads associated with the application program, wherein each thread in the plurality of parallel threads generates a separate command list in the plurality of command lists; and causing a first command list associated with a first thread included in the plurality of parallel threads to be executed by a processing unit based on a first processing state, wherein the first processing state includes a set of graphics parameters; after the processing unit executes the first command list, causing a second command list associated with a second thread included in the plurality of parallel threads to be executed by the processing unit based on the first processing state inherited from the first command list. 22. The computer system of claim 21 , wherein the processin

Assignees

Inventors

Classifications

  • Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

  • G06F9/461Primary

    Saving or restoring of program or task context · CPC title

  • G06F15/17Primary

    using an input/output type connection, e.g. channel, I/O port · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10169072B2 cover?
A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed…
Who is the assignee on this patent?
Duluk Jr Jerome F, Hall Jesse David, Moreton Henry Packard, and 2 more
What technology area does this patent fall under?
Primary CPC classification G06F9/461. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).