Memory device that performs internal copy operation

Patent metadata

Field	Value
Publication number	US-10169042-B2
Application number	US-201514852774-A
Country	US
Kind code	B2
Filing date	Sep 14, 2015
Priority date	Nov 24, 2014
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array including at least one bank that includes at least one block, each of the at least one block having a plurality of memory cell rows having memory cells therein; and
processing circuitry configured to,
receive, from an external source, an internal copy command along with a source address and a destination address associated therewith, the source address indicating a source bank of the at least one bank and a source block of the at least one block within the source bank, and the destination address indicating a destination bank of the at least one bank and a destination block of the at least one block within the destination bank,
compare one or more of (i) the source bank and the destination bank and (ii) the source block and the destination block,
generate one or more of a bank comparison signal and a block comparison signal based on a result of comparing the one or more of (i) the source bank with the destination bank and (ii) the source block with the destination block, the bank comparison signal indicating whether the source bank and the destination bank are a same bank or different banks, and the block comparison signal indicating whether the source block and the destination block are a same block or different blocks,
select a selected internal copy operation from among an internal block copy operation, an inter-bank copy operation or an internal bank copy operation based on the one or more of the bank comparison signal and the block comparison signal,
perform the selected internal copy operation on the memory cell array from the memory cells associated with the source address to the memory cells associated with the destination address, and
output a copy-done signal indicating that the selected internal copy operation is complete, if the selected internal copy operation is complete.

2. The memory device of claim 1 , wherein the processing circuitry is further configured to,
receive page size information associated with the selected internal copy operation from the external source, and
instruct the memory cell array to perform the selected internal copy operation based on the page size information.

3. The memory device of claim 2 , wherein, the processing circuitry is configured to instruct the memory cell array to perform the selected internal copy operation in units of one-page data, half-page data, or quarter-page data of one of the plurality of memory cell rows based on the page size information.

4. The memory device of claim 1 , wherein the processing circuitry comprises:
a first comparator configured to output the bank comparison signal based on a bank address associated with the source address and a bank address associated with the destination address; and
a second comparator configured to output the block comparison signal based on a block address associated with the source address and a block address associated with the destination address.

5. The memory device of claim 4 , wherein
the processing circuitry is configured to select the internal block copy operation as the selected internal copy operation, if the bank comparison signal and the block comparison signal indicate that the source address and the destination address are associated with the same bank and the same block, and
the internal block copy operation is an operation of writing, via a sense amplifier, data of the memory cells connected to a first memory cell row in the same block within the same bank to the memory cells connected to a second memory cell row in the same block within the same bank.

6. The memory device of claim 4 , wherein
the processing circuitry is configured to select the inter-bank copy operation as the selected internal copy operation, if the bank comparison signal indicates that the source address and the destination address are associated with the different banks, and
the inter-bank copy operation is an operation of writing, via a data path, data of the memory cells connected to a first memory cell row in a first bank to the memory cells connected to a second memory cell row in a second bank.

7. The memory device of claim 4 , wherein
the processing circuitry is configured to select the internal bank copy operation as the selected internal copy operation, if the bank comparison signal and the block comparison signal indicate that the source block and the source bank and the destination block and the destination bank are the same bank and the different blocks, and
the internal bank copy operation is an operation of writing, via first sense amplifiers of a first block and second sense amplifiers of a second block, data of the memory cells connected to a first memory cell row in the first block within the same bank to the memory cells connected to a second memory cell row in the second block within the same bank.

8. The memory device of claim 1 , wherein the processing circuitry is configured to store the copy-done signal in a Multi Purpose Register (MPR) of a mode register of the memory device.

9. The memory device of claim 8 , wherein the mode register is configured to output the copy-done signal according to a mode register read command.

10. The memory device of claim 8 , wherein the mode register is configured to output the copy-done signal via a data input/output (DQ) pin of the memory device.

11. The memory device of claim 8 , wherein the mode register is configured to output the copy-done signal via a dedicated pin included in the memory device.

12. A system comprising:
a memory controller configured to transmit an internal copy command along with a source address and a destination address associated therewith; and
a memory device including a memory cell array and processing circuitry, the memory cell array including at least one bank that includes at least one block, each of the at least one block having a plurality of memory cell rows, the processing circuitry configured to,
receive, from the memory controller, the internal copy command along with the source address and the destination address associated therewith, the source address indicating a source bank of the at least one bank and a source block of the at least one block within the source bank, and the destination address indicating a destination bank of the at least one bank and a destination block of the at least one block within the destination bank,
compare one or more of (i) the source bank and the destination bank and (ii) the source block and the destination block,
generate one or more of a bank comparison signal and a block comparison signal based on a result of comparing the one or more of (i) the source bank with the destination bank and (ii) the source block with the destination block, the bank comparison signal indicating whether the source bank and the destination bank are a same bank or different banks, and the block comparison signal indicating whether the source block and the destination block are a same block or different blocks,
select a selected internal copy operation from among an internal block copy operation, an inter-bank copy operation or an internal bank copy operation based on the one or more of the bank comparison signal and the block comparison signal,
perform the selected internal copy operation on the memory cell rows, and
output a copy-done signal indicating that the selected internal copy operation is complete, if the selected internal copy operation is complete.

13. The system of claim 12 , wherein
the memory controller is configured to transmit page size information associated with the selected internal copy operation, and
the processing circuitry of the memory devi

Assignees

• Sohn Young Soo
• Kim Sei Jin
• Park Kwang Il
• Kim Tae Young
• Park Chul Woo
• Samsung Electronics Co Ltd

Inventors

• Sohn Young-Soo
• Kim Sei-Jin
• Park Kwang-Il
• Kim Tae-Young
• Park Chul-Woo

Classifications

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G06F9/3004 Primary

  to perform operations on memory · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F15/785

  with decentralized control, e.g. smart memories · CPC title