Compiler method for generating instructions for vector operations in a multi-endian instruction set

Patent metadata

Field	Value
Publication number	US-10169014-B2
Application number	US-201414576710-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Dec 19, 2014
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias, along with at least one memory access instruction with a contrary endian bias. The compiler uses a code generation endian preference that matches the inherent computer system endian bias. The compiler generates instructions for vector instructions by determining whether the vector instruction has an endian bias that matches the code generation endian preference. When the endian bias of the vector instruction matches the code generation endian preference, the compiler generates one or more instructions for the vector instruction as normal. When the endian bias of the vector instruction does not match the code generation endian preference, the compiler generates instructions that include one or more vector element reverse instructions to fix the mismatch.

First claim

The invention claimed is:

1. A computer-implemented method executed by at least one processor for a compiler to process a plurality of instructions in a computer program, the method comprising the steps of:
specifying to the compiler a code generation endian preference;
the compiler reading the plurality of instructions;
the compiler selecting a vector instruction in the plurality of instructions;
the compiler determining when the vector instruction generates a vector load instruction that does not satisfy the code generation endian preference; and
when the vector instruction is a vector load instruction that does not satisfy the code generation endian preference, the compiler adding to the plurality of instructions in the computer program at least one vector element reverse instruction after the vector load instruction to correct a mismatch between an endian bias of the vector load instruction and the code generation endian preference.

2. The method of claim 1 further comprising:
the compiler determining when the vector instruction generates a vector store instruction that does not satisfy the code generation endian preference;
when the vector instruction is a vector store instruction that does not satisfy the code generation endian preference, the compiler adding to the plurality of instructions in the computer program at least one vector element reverse instruction before the vector store instruction to correct a mismatch between an endian bias of the vector store instruction and the code generation endian preference.

3. The method of claim 1 wherein the vector load instruction does not satisfy the code generation endian preference when the vector load instruction has a big endian bias and the code generation endian preference is little endian.

4. The method of claim 1 wherein the vector load instruction does not satisfy the code generation endian preference when the vector load instruction has a little endian bias and the code generation endian preference is big endian.

5. The method of claim 2 wherein the vector store instruction does not satisfy the code generation endian preference when the vector store instruction has a big endian bias and the code generation endian preference is little endian.

6. The method of claim 2 wherein the vector store instruction does not satisfy the code generation endian preference when the vector store instruction has a little endian bias and the code generation endian preference is big endian.

7. The method of claim 1 wherein each vector element reverse instruction reverses order of a plurality of elements of a vector register.

8. The method of claim 7 wherein the plurality of elements of the vector register comprises one of:
a plurality of bytes;
a plurality of halfwords;
a plurality of words;
a plurality of double-words;
a plurality of quadwords; and
a plurality of elements larger than quadwords.

9. A computer-implemented method executed by at least one processor for a compiler to process a plurality of instructions in a computer program, the method comprising the steps of:
specifying to the compiler a code generation endian preference;
selecting a vector instruction;
determining when the vector instruction is a vector load instruction that does not satisfy the code generation endian preference, wherein the vector load instruction does not satisfy the code generation endian preference when:
the vector load instruction has a big endian bias and the code generation endian preference is little endian; or
the vector load instruction has a little endian bias and the code generation endian preference is big endian;

when the vector instruction is a vector load instruction that does not satisfy the code generation endian preference, adding at least one vector element reverse instruction after the vector load instruction to correct a mismatch between an endian bias of the vector load instruction and the code generation endian preference;
determining when the vector instruction is a vector store instruction that does not satisfy the code generation endian preference, wherein the vector store instruction does not satisfy the code generation endian preference when:
the vector store instruction has a big endian bias and the code generation endian preference is little endian; or
the vector store instruction has a little endian bias and the code generation endian preference is big endian;

when the vector instruction is a vector store instruction that does not satisfy the code generation endian preference, adding at least one vector element reverse instruction before the vector store instruction to correct a mismatch between an endian bias of the vector store instruction and the code generation endian preference;
wherein each vector element reverse instruction reverses order of a plurality of elements of a vector register, wherein the plurality of elements of the vector register comprises one of:
a plurality of bytes;
a plurality of halfwords;
a plurality of words;
a plurality of double-words;
a plurality of quadwords; and
a plurality of elements larger than quadwords.

Assignees

• IBM

Inventors

• Gschwind Michael Karl
• Ji Jin Song
• Mcintosh Ronald I
• Schmidt William J

Classifications

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F8/447 Primary

  Target code generation · CPC title

• G06F9/30025

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title