Memory system and operating method thereof

Patent metadata

Field	Value
Publication number	US-10168907-B2
Application number	US-201715700539-A
Country	US
Kind code	B2
Filing date	Sep 11, 2017
Priority date	Nov 30, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

a memory system may include: a memory device including a plurality of memory dies each having a plurality of memory blocks; and a controller suitable for performing one or more of data defragmentation and data remapping operations for a target transaction group in the memory device in response to a request message provided from a host, transmitting a completion message to the host as a response to the request message, and receiving an access to the transaction group, from the host.

First claim

What is claimed is:

1. A memory system comprising:
a memory device including a plurality of memory dies each having a plurality of memory blocks; and a controller suitable for performing one or more of data defragmentation and data remapping operations for a target transaction group in the memory device in response to a request message provided from a host, transmitting a completion message to the host as a response to the request message, and receiving an access to the transaction group, from the host, wherein the request message includes a data array having information on data splits of the target transaction group, and address lists of the target transaction group, wherein the request message further includes a header having a flag indicating type information of the data defragmentation and data remapping operations, wherein the type information indicates at last one among a general mode, a fast mode, an optimized mode, a cold mode and a hot mode.

2. The memory system according to claim 1 , wherein the header further has a total size of the target transaction group.

3. The memory system according to claim 1 , wherein the header further has a split count of the target transaction group.

4. The memory system according to claim 1 , wherein the information on data splits of the target transaction group of the data array has start addresses and address sizes for respective data splits of the target transaction group.

5. The memory system according to claim 1 , wherein the controller identifies a data distribution of the target transaction group in the memory device through the header, the data array and the address lists of the target transaction group.

6. The memory system according to claim 5 , wherein the controller performs the one or more of data defragmentation and data remapping operations for the data splits of the target transaction group with memory blocks of memory dies coupled to the same channel or memory blocks of the same cell type.

7. The memory system according to claim 5 , wherein the controller performs only a data remapping operation for metadata of the data splits of the target transaction group.

8. A method for operating a memory system, comprising:
receiving, from a host, a request message with respect to a memory device including a plurality of memory dies each having a plurality of memory blocks; and performing one or more of data defragmentation and data remapping operations for a target transaction group in the memory device in response to the request message, wherein the request message includes a data array having information on data splits of the target transaction group, and address lists of the target transaction group, wherein the request message further includes a header having a flag indicating type information of the data defragmentation and data remapping operations, wherein the type information indicates at last one among a general mode, a fast mode, an optimized mode, a cold mode and a hot mode.

9. The method according to claim 8 , wherein the header further has a total size of the target transaction group.

10. The method according to claim 8 , wherein the header further has a split count of the target transaction group.

11. The method according to claim 8 , wherein the information on data splits of the target transaction group of the data array has start addresses and address sizes for respective data splits of the target transaction group.

12. The method according to claim 8 , wherein the performing includes identifying a data distribution of the target transaction group in the memory device through the header, the data array and the address lists of the target transaction group.

13. The method according to claim 10 , wherein the one or more of data defragmentation and data remapping operations are performed for the data splits of the target transaction group with memory blocks of memory dies coupled to the same channel or memory blocks of the same cell type.

14. The method according to claim 10 , wherein only the data remapping operation is performed for metadata of the data splits of the target transaction group.

Assignees

• Sk Hynix Inc

Inventors

• Chang Gi-Seob
• SHIN Soong-Sun

Classifications

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title