Liquid crystal display panel having dual capacitors connected in parallel to shift register unit and array substrate thereof

Patent metadata

Field	Value
Publication number	US-10168593-B2
Application number	US-201514433655-A
Country	US
Kind code	B2
Filing date	Jan 6, 2015
Priority date	Dec 30, 2014
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Disclosed are a liquid crystal display panel and an array substrate thereof. The array substrate includes a substrate body, a first metal layer, a first dielectric layer, and a second dielectric layer, an insulating layer, and an electrode layer. The first metal layer, the first dielectric layer, and the second metal layer form a first capacitor; the second metal layer, the insulating layer, and the electrode layer form a second capacitor; the electrode layer is connected with the first metal layer through a channel hole penetrating through the first dielectric layer and the insulating layer, so that the first capacitor is connected with the second capacitor in parallel. Through the above way, the area of a gate driver on array (GOA) circuit on the array substrate can be reduced, which is beneficial for the narrow frame design of the liquid crystal display panel.

First claim

What is claimed is:

1. An array substrate, comprising: a substrate body, a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, an electrode layer, which are arranged on the substrate body; the first metal layer, the first dielectric layer, and the second metal layer forming a first capacitor; the second metal layer, the insulating layer, and the electrode layer forming a second capacitor; the electrode layer being connected with the first metal layer through a channel hole penetrating through the first dielectric layer and the insulating layer, so that the first capacitor is connected with the second capacitor in parallel;
wherein the array substrate further comprises a thin-film transistor arranged on the substrate body and a shift register unit located at a non-display area, the first capacitor and the second capacitor are connected with the shift register unit in parallel, the thin-film transistor comprising a gate electrode, a source electrode, and a drain electrode, the gate electrode and the first metal layer are formed synchronously, the second metal layer and a source-drain electrode layer composed of the source electrode and the drain electrode are formed synchronously, the first dielectric layer of the first capacitor and the first dielectric layer provided between the source-drain electrode layer and the gate electrode are formed synchronously;
wherein the first capacitor and the second capacitor that are connected with the shift register unit are separate from the source electrode and the drain electrode of the thin-film transistor.

2. The array substrate as claimed in claim 1 , wherein the projected area of the first metal layer on the substrate body along the direction vertical to the substrate body is larger than that of the second metal layer, and the channel hole is arranged outside the projected area corresponding to the second metal layer.

3. The array substrate as claimed in claim 1 , wherein the array substrate comprises a first area and a second area, and the thin-film transistor is located at the first area, and the electrode layer is arranged on the insulating layer of the second area.

4. The array substrate as claimed in claim 3 , wherein the thin-film transistor further comprises a semiconductor layer provided on the substrate body, a second dielectric layer is provided between the semiconductor layer and the gate electrode, the first metal layer is arranged on the second dielectric layer, and the source electrode and the drain electrode penetrate the first dielectric layer and the second dielectric layer and are connected with the semiconductor layer.

5. The array substrate as claimed in claim 3 , wherein the thin-film transistor further comprises a semiconductor layer provided between the gate electrode and the source-drain electrode, the second dielectric layer is provided between the semiconductor layer and the gate electrode, the first dielectric layer is provided between the semiconductor layer and the source-drain electrode, and the source electrode and the drain electrode penetrate the first dielectric layer and are connected with the semiconductor layer.

6. An array substrate, comprising: a substrate body, a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, an electrode layer, which are arranged on the substrate body; the first metal layer, the first dielectric layer, and the second metal layer forming a first capacitor; the second metal layer, the insulating layer, and the electrode layer forming a second capacitor; the electrode layer being connected with the first metal layer through a channel hole penetrating through the first dielectric layer and the insulating layer, so that the first capacitor is connected with the second capacitor in parallel;
wherein the array substrate further comprises a shift register unit located at a non-display area, and the first capacitor and the second capacitor are connected with the shift register unit in parallel.

7. The array substrate as claimed in claim 6 , wherein the projected area of the first metal layer on the substrate body along the direction vertical to the substrate body is larger than that of the second metal layer, and the channel hole is arranged outside the projected area corresponding to the second metal layer.

8. The array substrate as claimed in claim 6 , wherein the array substrate further comprises a thin-film transistor arranged on the substrate body, the thin-film transistor comprises a gate electrode, a source electrode, and a drain electrode, the gate electrode and the first metal layer are formed synchronously, the second metal layer and a source-drain electrode layer composed of the source electrode and the drain electrode are formed synchronously, the first dielectric layer of the first capacitor and the first dielectric layer provided between the source-drain electrode layer and the gate electrode are formed synchronously.

9. The array substrate as claimed in claim 8 , wherein the array substrate comprises a first area and a second area, and the thin-film transistor is located at the first area, and the electrode layer is arranged on the insulating layer of the second area.

10. The array substrate as claimed in claim 9 , wherein the thin-film transistor further comprises a semiconductor layer provided on the substrate body, and a second dielectric layer is provided between the semiconductor layer and the gate electrode, and the first metal layer is arranged on the second dielectric layer, and the source electrode and the drain electrode penetrate the first dielectric layer and the second dielectric layer and are connected with the semiconductor layer.

11. The array substrate as claimed in claim 9 , wherein the thin-film transistor further comprises a semiconductor layer provided between the gate electrode and the source-drain electrode layer, and the second dielectric layer is provided between the semiconductor layer and the gate electrode, and the first dielectric layer is provided between the semiconductor layer and the source-drain electrode layer, and the source electrode and the drain electrode penetrate the first dielectric layer and are connected with the semiconductor layer.

12. The array substrate as claimed in claim 8 , wherein the distance between the second metal layer and the substrate body is the same as the distance between the source-drain electrode layer and the substrate body.

13. The array substrate as claimed in claim 8 , wherein the thickness of the gate electrode is the same as the thickness of the first metal layer, and the thickness of the source-drain electrode layer is the same as the thickness of the second metal layer.

14. A liquid crystal display panel, comprising: a color film substrate arranged opposite to an array substrate, and a liquid crystal layer provided between the color film substrate and the array substrate, the array substrate comprising: a substrate body, a first metal layer, a first dielectric layer, a second metal layer, an insulating layer, an electrode layer, which are arranged on the substrate body; the first metal layer, the first dielectric layer, and the second metal layer forming a first capacitor; the second metal layer, the insulating layer, and the electrode layer forming a second capacitor; the electrode layer being connected with the first metal layer through a channel hole penetrating through the first dielectric layer and the insulating layer, so that the first capacitor is connected with the second capacitor in parallel;
wherein the array substrate further comprises a shift register unit located at a non-display area, and the fi

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelectronics Co Ltd

Inventors

• Hao Sikun

Classifications

• H01L27/1255

  Electricity · mapped topic

• G02F2001/13685

  Physics · mapped topic

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F2001/136295

  Physics · mapped topic

• G02F1/13454

  Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence) · CPC title