Method of manufacturing optical input/output device

Patent metadata

Field	Value
Publication number	US-10168474-B2
Application number	US-201715607726-A
Country	US
Kind code	B2
Filing date	May 30, 2017
Priority date	May 23, 2013
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

First claim

What is claimed is:

1. A method of manufacturing an optical input/output device, the method comprising:
providing a bulk silicon substrate;
monolithically integrating a vertical-input light detection element on a portion of the bulk silicon substrate; and
monolithically integrating a vertical-output light source element on another portion of the bulk silicon substrate,
wherein monolithically integrating the vertical-output light source element comprises:
forming an element passivation layer covering the vertical-input light detection element on the portion of the bulk silicon substrate;
bonding a wafer including a III-V compound semiconductor light source active layer on the III-V compound semiconductor substrate to the other portion of the bulk silicon substrate;
removing the III-V compound semiconductor substrate;
device-fabricating the III-V compound semiconductor light source active layer to form the vertical-output light source element on the bulk silicon substrate; and
forming a passivation layer on the vertical-input light detection element and the vertical-output light source element,
wherein the portion of the bulk silicon substrate is on a same plane of the bulk silicon substrate as the other portion of the bulk silicon substrate.

2. The method of claim 1 , further comprising:
etching the passivation layer to form holes exposing the vertical-input light detection element and the vertical-output light source element;
forming optical vias in the holes, respectively;
forming horizontal optical waveguides onto the passivation layer, the horizontal optical waveguides coupled to the optical vias; and
forming a passive optical circuit on the passivation layer, the passive optical circuit coupled to the horizontal optical waveguide, and the passive optical circuit including optical multiplexer/demultiplexer (MUX/DEMUX), an optical switch, or a grating coupler.

3. The method of claim 1 , wherein the same plane of the bulk silicon substrate is an upper surface of the bulk silicon substrate.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Kim Gyungock
• Park Hyundai
• Kim In Gyoo
• Kim Sang Hoon
• Jang Ki Seok
• Kim Sang Gi
• Joo Jiho
• Choi Yongseok
• Kwon Hyuk Je
• Park Jaegyu
• Kim Sun Ae
• Oh Jin Hyuk
• Kwack Myung Joon

Classifications

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• G02B6/4214

  the intermediate optical element having redirecting reflective means, e.g. mirrors, prisms for deflecting the radiation from horizontal to down- or upward direction toward a device (G02B6/4246 takes precedence) · CPC title

• G02B6/4206

  Optical features (G02B6/4207, G02B6/421 take precedence) · CPC title

• G02B6/13

  Integrated optical circuits characterised by the manufacturing method · CPC title