Circuit boards and electronic packages with embedded tamper-respondent sensor

Patent metadata

Field	Value
Publication number	US-10168185-B2
Application number	US-201514941908-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Sep 25, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.

First claim

What is claimed is:

1. A method of fabricating an electronic circuit comprising:
providing a multilayer circuit board;
providing an enclosure mounted to the multilayer circuit board within a groove in the multilayer circuit board; and
providing a tamper-respondent sensor embedded within the multilayer circuit board, the tamper-respondent sensor defining, at least in part, a secure volume associated with the multilayer circuit board, and comprising:
multiple tamper-respondent layers within the multilayer circuit board, the multiple tamper-respondent layers being spaced apart, parallel layers within the multilayer circuit board that facilitate defining the secure volume, at least in part, within the multilayer circuit board, and the multiple tamper-respondent layers comprising:
at least one tamper-respondent picture frame-type layer encircling the secure volume within the multilayer circuit board, a tamper-respondent picture frame-type layer of the at least one tamper-respondent picture frame-type layer comprising one or more conductive trace lines extending horizontally around the tamper-respondent picture frame-type layer within the multilayer circuit board and encircling the secure volume within the multilayer circuit board, wherein the one or more conductive trace lines of the tamper-respondent picture frame-type layer encircling the secure volume within the multilayer circuit board are encircled or intersected by the groove in the multilayer circuit board; and
at least one tamper-respondent mat layer forming a base of the secure volume within the multilayer circuit board, the at least one tamper-respondent picture frame-type layer being disposed over the at least one tamper-respondent mat layer.

2. The method of claim 1 , wherein at least one tamper-respondent layer of the multiple tamper-respondent layers comprises multiple, separate tamper-respondent circuit zones, and wherein the multiple tamper-respondent layers, including the multiple, separate tamper-respondent circuit zones of the at least one tamper-respondent layer, are electrically connected to monitor circuitry within the secure volume associated with the multilayer circuit board.

3. The method of claim 1 , wherein at least two tamper-respondent layers of the multiple tamper-respondent layers each comprise multiple, separate tamper-respondent circuit zones, and wherein at least two tamper-respondent circuit zones within different tamper-respondent layers of the at least two tamper-respondent layers are electrically connected to a common monitor circuit within the secure volume associated with the multilayer circuit board.

4. The method of claim 3 , wherein the at least one tamper-respondent picture frame-type layer of the multiple tamper-respondent layers defines, at least in part, a side portion of the secure volume within the multilayer circuit board.

5. The method of claim 1 , wherein the multilayer circuit board comprises an external signal layer embedded within the multilayer circuit board, the external signal layer electrically connecting to at least one electronic component within the secure volume, and residing, at least in part, over a tamper-respondent mat layer of the at least one tamper-respondent mat layer.

6. The method of claim 1 , wherein the multiple tamper-respondent layers within the multilayer circuit board comprise at least two tamper-respondent picture frame-type layers, the at least two tamper-respondent picture frame-type layers defining, at least in part, a periphery of the secure volume where extending into the multilayer circuit board.

7. The method of claim 1 , wherein the at least one tamper-respondent picture frame-type layer embedded within the multilayer circuit board defines a periphery of the secure volume within the multilayer circuit board.

8. The method of claim 1 , wherein the tamper-respondent mat layer of the at least one tamper-respondent mat layer extends from below the secure volume outward past the groove in the multilayer circuit board.

Assignees

• IBM

Inventors

• Brodsky William L
• Dragone Silvio
• Krabbenhoft Roger S
• Long David C
• Oggioni Stefano S
• Peets Michael T
• Santiago-Fernandez William

Classifications

• H05K2201/096

  Vertically aligned vias, holes or stacked vias · CPC title

• H05K2201/09263

  Meander · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K1/0275 Primary

  Security details, e.g. tampering prevention or detection · CPC title

• G06F21/86

  Secure or tamper-resistant housings · CPC title