Communication apparatus with multiple buffers and control thereof

Patent metadata

Field	Value
Publication number	US-10164916-B2
Application number	US-201615220435-A
Country	US
Kind code	B2
Filing date	Jul 27, 2016
Priority date	Aug 5, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A packet communication apparatus is configured to relay packets transmitted and received between information processing apparatuses. The packet communication apparatus includes: a network interface connectable to a network; a CPU to be a destination of at least one of a plurality of packets to be received through the network interface; a first buffer configured to hold the packets destined to the CPU in order to output the packets to the CPU; a second buffer having a plurality of planes and configured to hold copies of the packets destined to the CPU held in the first buffer in one of the plurality of planes; and a reception history controller configured to store a copy of a packet to a specified plane of the second buffer or to save copies of packets held in the second buffer to another storage area based on usage of the first buffer.

First claim

What is claimed is:

1. A packet communication apparatus configured to relay packets transmitted and received between information processing apparatuses, the packet communication apparatus comprising:
a physical line controller connectable to a network;
a CPU to be a destination of at least one of a plurality of packets to be received through the network interface; and
a frame controller that includes a CPU-destined frame reception buffer, and a reception history buffer, and the frame controller is configured to:
hold the packets destined to the CPU in the CPU-destined frame reception buffer in order to output the packets to the CPU,
hold copies of the packets destined to the CPU held in the CPU-destined frame reception buffer in a first plane of the reception history buffer,
monitor the usage of the CPU-destined frame reception buffer,
change from the first plane to a second plane of the reception history buffer to store newly received copies of the packets destined to the CPU held in the CPU-destined frame reception buffer when the usage reaches a first threshold, and
save the copies of the packets held in the reception history buffer to another storage area different than the CPU-destined frame reception buffer and the reception history buffer when the usage reaches a second threshold higher than the first threshold.

2. The packet communication apparatus according to claim 1 , wherein each the first plane and the second plane of the reception history buffer has a same capacity as the CPU-destined frame reception buffer.

3. The packet communication apparatus according to claim 1 , wherein the frame controller is further configured to:
overwrite the copy of one packet already held in the first plane of the reception history buffer with a copy of another packet destined to the CPU by using the first plane of the reception history buffer as a ring buffer in a case where the usage of the first buffer does not reach the first threshold, and
change to the second plane and store the newly received copies of the packets to the second plane in a case where the first plane does not have enough free space when the usage of the first buffer has reached the first threshold.

4. The packet communication apparatus according to claim 3 , wherein the frame controller is further configured to overwrite the copy of one packet already held in the first plane with a copy of another packet destined to the CPU by using the first plane as the ring buffer in a case where the first plane does not have enough free space when the usage of the first buffer falls below a third threshold after reaching the first threshold.

5. The packet communication apparatus according to claim 1 , wherein the frame controller further includes a CPU-originated frame transmission buffer and a transmission history buffer having a plurality of planes, and
wherein the frame controller is further configured to
hold packets originated from the CPU in the CPU-originated frame transmission buffer in order to output the packets from the CPU to a network via the network interface,
hold copies of the packets originated from the CPU held in the third buffer in the plurality of planes of the transmission history buffer based on usage of the CPU-originated frame transmission buffer.

6. A packet communication apparatus configured to relay packets transmitted and received between information processing apparatuses, the packet communication apparatus comprising:
a physical line controller connectable to a network;
a CPU to be either a destination of at least one of a plurality of packets to be received through the network interface or a source of at least one of a plurality of packets to be sent out through the network interface; and
a frame controller that includes a frame reception buffer, and a reception history buffer, a frame transmission buffer, and a transmission history buffer, and the frame controller is configured to:
hold received incoming packets in the reception buffer in order to output the held incoming packets to the CPU,
hold outgoing packets output from the CPU in the transmission buffer in order to send the held outgoing packets out to the network,
hold copies of the outgoing packets in an area determined based on a status of the held outgoing packets of the transmission buffer,
hold copies of the packets destined to the CPU held in the frame reception buffer in a first plane of the reception history buffer,
monitor the usage of the frame reception buffer,
change from the first plane to a second plane of the reception history buffer to store newly received copies of the packets destined to the CPU held in the frame reception buffer when the usage reaches a first threshold, and
save the copies of the packets held in the reception history buffer to another storage area different than the frame reception buffer, the reception history buffer, the frame transmission buffer, and the transmission history buffer when the usage reaches a second threshold higher than the first threshold.

Assignees

• Alaxala Networks Corp

Inventors

• Nishikawa Kouichi

Classifications

• H04L49/9031 Primary

  Wraparound memory, e.g. overrun or underrun detection · CPC title

• H04L49/9047

  including multiple buffers, e.g. buffer pools · CPC title

• H04L49/252

  Store and forward routing · CPC title

• H04L47/29

  using a combination of thresholds · CPC title

• H04L49/1523

  Parallel switch fabric planes · CPC title