Encoding circuit, method for transmitting data over a data bus, and radio communication device

Patent metadata

Field	Value
Publication number	US-10164732-B2
Application number	US-201514748293-A
Country	US
Kind code	B2
Filing date	Jun 24, 2015
Priority date	Jun 24, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

An encoding circuit for selecting a transmit data symbol for transmission over a data bus may include an alternate symbol generation circuit configured to generate an alternate data symbol based on an encoded data symbol scheduled for transmission over the data bus and a decision circuit configured to select the encoded data symbol or the alternate data symbol as the transmit symbol based on a plurality of phasors. The decision circuit may include a plurality of phasor generation circuits configured to generate the plurality of phasors based on the encoded data symbol and a plurality of target frequencies.

First claim

What is claimed is:

1. An encoding circuit configured to select a transmit data symbol for transmission over a data bus comprising:
an alternate symbol generation circuit configured to generate an alternate data symbol based on an encoded data symbol scheduled for transmission over the data bus; and
a decision circuit configured to select the encoded data symbol or the alternate data symbol as the transmit data symbol based on a plurality of phasors, wherein the decision circuit comprises:
a plurality of edge detection circuits configured to generate a plurality of edge-detected representations of the encoded data symbol; and
a plurality of phasor generation circuits configured to generate the plurality of phasors based on the encoded data symbol and a plurality of target frequencies; and
wherein each of the plurality of phasor generation circuits is configured to calculate a phasor of the encoded data symbol or the respective edge-detected representation of the plurality of edge-detected representations according to a mode control signal.

2. The encoding circuit of claim 1 , wherein the decision circuit is configured to select the encoded data symbol or the alternate data symbol as the transmit data symbol based on whether transmission of the encoded data symbol or the alternate data symbol will reduce a cumulative phasor over time at one at one or more of the plurality of target frequencies.

3. The encoding circuit of claim 1 , wherein a first phasor generation circuit of the plurality of phasor generation circuits is configured to generate a first phasor of the plurality of phasors by calculating the phasor of the encoded data symbol at a first target frequency of the plurality of target frequencies.

4. The encoding circuit of claim 3 , wherein a second phasor generation circuit of the plurality of phasor generation circuits is configured to generate a second phasor of the plurality of phasors by calculating the phasor of the encoded data symbol at a second target frequency of the plurality of target frequencies.

5. The encoding circuit of claim 4 , wherein the decision circuit is configured to select the encoded data symbol or the alternate data symbol as the transmit data symbol based on the first phasor and the second phasor.

6. The encoding circuit of claim 1 , wherein the alternate symbol generation circuit comprises at least one inverting circuit,
and wherein the alternate symbol generation circuit is configured to generate the alternate data symbol by logically inverting at least one bit of the encoded data symbol.

7. An encoding circuit configured to select a transmit data symbol for transmission over a data bus comprising:
an alternate symbol generation circuit configured to generate an alternate data symbol based on the encoded data symbol scheduled for transmission over the data bus; and
a decision circuit configured to select the encoded data symbol or the alternate data symbol as the transmit data symbol based on a first phasor,
wherein the decision circuit comprises:
an edge detection circuit configured to generate an edge-detected data symbol based on the encoded data symbol; and
a phasor generation circuit configured to determine the first phasor based on the edge-detected data symbol and a target frequency; and
wherein the phasor generation circuit is configured to calculate a phasor of the encoded data symbol or the edge-detected data symbol according to a mode control signal.

8. The encoding circuit of claim 7 , wherein the decision circuit is configured to select the encoded data symbol or the alternate data symbol as the transmit data symbol based on whether transmission of the encoded data symbol or the alternate data symbol will reduce a cumulative phasor over time at the target frequency.

9. The encoding circuit of claim 7 , wherein the decision circuit further comprises:
an additional phasor generation circuit configured to determine a second phasor based on the edge-detected data symbol and an additional target frequency.

10. The encoding circuit of claim 9 , wherein the decision circuit is configured to select the encoded data symbol or the alternate data symbol as the transmit data symbol based on the first phasor and the second phasor.

11. The encoding circuit of claim 7 , wherein the alternate symbol generation circuit is configured to invert bits at odd-numbered positions of the encoded data symbol.

12. The encoding circuit of claim 7 , wherein the decision circuit further comprises:
an additional edge detection circuit configured to generate an additional edge-detected data symbol based on the encoded data symbol; and
an additional phasor generation circuit configured to determine a second phasor based on the additional edge-detected data symbol and an additional target frequency,
wherein the decision circuit is configured to select the encoded data symbol or the alternate data symbol based on the first phasor and the second phasor.

13. An encoding circuit configured to select a transmit data symbol for transmission over a data bus comprising:
an alternate symbol generation circuit configured to generate an alternate data symbol based on an encoded data symbol scheduled for transmission over the data bus; and
a decision circuit configured to receive the encoded data symbol and the alternate data symbol and further configured to select the encoded data symbol or the alternate data symbol as the transmit data symbol based on a first phasor and a second phasor of a plurality of phasors; wherein the decision circuit comprises:
a plurality of edge detection circuits configured to generate a plurality of edge-detected representations of the encoded data symbol; and
a plurality of phasor generation circuits configured to generate the plurality of phasors based on the encoded data symbol and a plurality of target frequencies; and
wherein each of the plurality of phasor generation circuits is configured to calculate a phasor of the encoded data symbol or the respective edge-detected representation of the plurality of edge-detected representations according to a mode control signal.

14. The encoding circuit of claim 13 , wherein the decision circuit is configured to select the encoded data symbol or the alternate symbol as the transmit data symbol based on the plurality of phasors.

15. The encoding circuit of claim 14 , wherein a first phasor generation circuit of the plurality of phasor generation circuits is configured to generate the first phasor of the plurality of phasors by calculating the phasor of the encoded data symbol at a first target frequency of a plurality of target frequencies.

16. The encoding circuit of claim 15 , wherein a second phasor generation circuit of the plurality of phasor generation circuits is configured to generate the second phasor of the plurality of phasors by calculating the phasor of the encoded data symbol at a second target frequency of the plurality of target frequencies.

17. The encoding circuit of claim 13 , wherein the alternate symbol generation circuit comprises at least one inverting circuit,
and wherein the alternate symbol generation circuit is configured to generate the alternate data symbol by logically inverting at least one bit of the encoded data symbol.

18. An encoding circuit configured to select a transmit data symbol for transmission over a data bus comprising:
an alternate symbol generation circuit configured to generate an alternate data symbol based on the encoded data symbol scheduled for transmission over the data bus; and
a decision circuit configu

Assignees

• Intel Ip Corp

Inventors

• Schultz Christoph
• Kesling William Dawson
• Mann Eytan

Classifications

• H04L1/0011 Primary

  applied to payload information · CPC title

• H04L25/08

  Modifications for reducing interference; Modifications for reducing effects due to line faults {; Receiver end arrangements for detecting or overcoming line faults} · CPC title

• H04L25/0276 Primary

  Arrangements for coupling common mode signals · CPC title

• H03K19/00346

  Modifications for eliminating interference or parasitic voltages or currents · CPC title

• H04L25/49

  using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} · CPC title