Low voltage transmitter with variable output swing

Patent metadata

Field	Value
Publication number	US-10164635-B2
Application number	US-201113993675-A
Country	US
Kind code	B2
Filing date	Dec 16, 2011
Priority date	Dec 16, 2011
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Described herein are apparatus, system, and method for improving output signal voltage swing of a voltage mode transmitter (Tx) driver. The Tx driver may use a single power supply which is the same as the power supply of the core processor. The apparatus comprises: a voltage mode driver coupled to an output node; a switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver; and a bias generator to bias the switching current source.

First claim

I claim:

1. An apparatus comprising:
a voltage mode driver;
an output node coupled to the voltage mode driver to output a signal; and
a switching current source coupled to the output node, the switching current source being coupled to a power supply node to add a current to the output node, to increase a voltage swing of the signal on the output node, while the signal on the output node is driven by the voltage mode driver, wherein the output node is located between the switching current source and the voltage mode driver.

2. The apparatus of claim 1 further comprises:
a bias generator to bias the switching current source.

3. The apparatus of claim 2 , wherein the bias generator is a replica bias circuit to provide adjustable bias voltages for the switching current source.

4. The apparatus of claim 1 , wherein the switching current source comprises:
a first current source, coupled to the output node, to increase the voltage swing of the signal on the output node by raising a logical high level of the signal.

5. The apparatus of claim 4 , wherein the switching current source comprises:
a second current source, coupled to the output node, to increase the voltage swing of the signal by lowering a logical low level of the signal.

6. The apparatus of claim 5 , wherein the voltage mode driver includes pull-up and pull-down devices.

7. The apparatus of claim 5 , wherein the second current source is operable to sink the current, to lower the logical low level of the signal, from the output node to a ground node when a pull-down device is on.

8. The apparatus of claim 5 , wherein the second current source comprises:
a first N-transistor, coupled to a ground node, to receive a signal to be driven on the output node.

9. The apparatus of claim 8 , wherein the second current source comprises:
a second N-transistor, coupled in series with the first N-transistor, to receive a bias voltage from a bias generator.

10. The apparatus of claim 4 , wherein the first current source is operable to inject the current, to raise the logical high level of the signal, from the power supply node to the output node when a pull-up device is on.

11. The apparatus of claim 4 , wherein the first current source comprises: a first P-transistor, coupled to the power supply node, to receive a signal to be driven on the output node.

12. The apparatus of claim 11 , wherein the first current source comprises:
a second P-transistor, coupled in series with the first P-transistor, to receive a bias voltage from a bias generator.

13. The apparatus of claim 1 , wherein the signal driven by the voltage mode driver is a high-speed (HS) GEAR rate signal compatible with the MIPI® M-PHY(SM) standard.

14. A method comprising:
receiving, by a voltage mode driver, an input signal for transmission on an output node;
driving a signal, based on the input signal, by the voltage mode driver for output to the output node; and
adding a current from a power supply node to the output node to increase a voltage swing of the signal on the output node, by a switching current source coupled to the power supply node and the output node while the signal on the output node is driven by the voltage mode driver, wherein the output node is located between the switching current source and the voltage mode driver.

15. The method of claim 14 further comprises:
providing a bias to the switching current source to increase the voltage
swing of the signal on the output node, wherein increasing the voltage swing of the signal on the output node, by the switching current source coupled to the output node, comprises:
injecting the current from the power supply node to the output node when the input signal to the voltage mode driver is a logical low, or
sinking the current from the output node to a ground node when the input signal to the voltage mode driver is a logical high.

16. A system comprising:
a wireless interface; and
a transmitter, communicatively coupled to the wireless interface, the transmitter comprising:
a voltage mode driver;
an output node coupled to the voltage mode driver to output a signal;
a switching current source coupled to the output node, the switching current source being coupled to a power supply node to add a current to the output node, to increase a voltage swing of the signal on the output node while the signal on the output node is driven by the voltage mode driver, wherein the output node is located between the switching current source and the voltage mode driver; and
a bias generator to bias the switching current source to provide adjustable bias voltages for the switching current source; and
a display unit.

17. The system of claim 16 , wherein the switching current source comprises:
a first current source, coupled to the output node, to increase the voltage swing of the signal on the output node by raising a logical high level of the signal; and
a second current source, coupled to the output node, to increase the voltage swing of the signal by lowering a logical low level of the signal.

18. The system of claim 17 , wherein the voltage mode driver includes pull-up and pull-down devices, wherein the first current source is operable to inject the current, to raise the logical high level of the signal, from the power supply node to the output node when a pull-up device is on, and
wherein the second current source is operable to sink the current, to lower the logical low level of the signal, from the output node to a ground node when a pull-down device is on.

19. The system of claim 17 , wherein the first current source comprises:
a first P-transistor, coupled to the power supply node, to receive a signal to be driven on the output node; and
a second P-transistor, coupled in series with the first P-transistor, to receive a bias voltage from a bias generator.

20. The system of claim 17 , wherein the second current source comprises:
a first N-transistor, coupled to a ground node, to receive a signal to be driven on the output node; and
a second N-transistor, coupled in series with the first N-transistor, to receive a bias voltage from a bias generator.

21. The system of claim 16 , wherein the signal driven by the voltage mode driver is a high-speed (HS) GEAR rate signal compatible with the MIPI® M-PHY(SM) standard.

22. The system of claim 16 further comprises:
a receiver coupled to the transmitter via a transmission medium, wherein the receiver is a MIPI® M-PHY(SM) receiver which is operable to receive highspeed (HS) GEAR rate signals.

23. The system of claim 16 , wherein the transmitter and a corresponding receiver are compliant with at least one of the standards:
Industry Processor Interface (MIPI®);
Peripheral Component Interconnect Express (PCIe);
Serial Advanced Technology Attachment (SATA);
Serial Attached SCSI (SAS);
Double Data Rate x (DDRx), were ‘x’ is an integer;
High-Definition Multimedia Interface (HDMI); or
Universal Serial Bus x (USBx), where ‘x’ is an integer.

24. The system of claim 16 , wherein the display unit is a touch pad of a touch screen.

25. The system of claim 16 , wherein the transmitter is a MIPI® M-PHY(SM) transmitter which is operable to receive high-speed (HS) GEAR rate signals.

Assignees

• Song Hongjiang
• Intel Corp

Inventors

• Song Hongjiang

Classifications

• G06F1/32

  Means for saving power · CPC title

• H04L25/0276

  Arrangements for coupling common mode signals · CPC title

• H03K19/017509 Primary

  Interface arrangements · CPC title