Electrostatic discharge protection

Patent metadata

Field	Value
Publication number	US-10164425-B2
Application number	US-201615083699-A
Country	US
Kind code	B2
Filing date	Mar 29, 2016
Priority date	Mar 29, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Circuits and methods concerning voltage surge protection are disclosed. In an example embodiment, an apparatus includes a switching circuit configured to enable a current path between a first node and a second node in a first mode and disable the current path in a second mode. A biasing circuit configured to, in the surge protection mode, prevent a voltage surge at the first node from enabling the current path to the second node by biasing a voltage of the control node.

First claim

What is claimed is:

1. An apparatus, comprising:
a switching circuit configured and arranged to enable a current path between a first node and a second node in a first mode and disable the current path in a second mode;
a biasing circuit configured to, in a second mode, prevent a voltage surge at the first node from enabling the current path to the second node by biasing a voltage of a control node,
wherein the switching circuit is configured to
operate in the first mode in response to a voltage of the control node relative to a voltage of the first node exceeding a threshold voltage, and
operate in the second mode in response to the voltage of the control node relative to the voltage of the first node being less than the threshold voltage,
wherein in the second mode the switching circuit is configured and arranged to disable the current path; and

the biasing circuit configured to, in the second mode, prevent a negative surge at the first node from enabling the current path to the second node by biasing the control node to reduce the voltage of the control node.

2. The apparatus of claim 1 , wherein
the switching circuit includes a transistor having a source and a drain electrically connected in the current path and a gate electrically connected to the control node;
the transistor is configured to enable the current path in response to a gate-source voltage exceeding the threshold voltage and disable the current path in response to the gate-source voltage being less than the threshold voltage; and
the biasing circuit is configured to reduce the voltage of the gate, in response to the first node having a voltage below an operating voltage range of the switching circuit, by an amount sufficient to prevent the gate-source voltage from exceeding the threshold voltage.

3. The apparatus of claim 2 , wherein
the biasing circuit includes an n-type transistor having a drain electrically connected to the control node, a source electrically connected to the first node, and a gate electrically connected to a ground voltage.

4. The apparatus of claim 3 , wherein
the first mode corresponds to an operation of providing power and/or a charge current, and
the second mode corresponds to an operation of providing surge protection.

5. The apparatus of claim 2 , wherein the biasing circuit further includes
a first resistor having a first end connected to the drain of an n-type transistor and a second end connected to an output of a driver circuit; and
a second resistor having a first end connected to the source of the n-type transistor and a second end connected to the first node.

6. The apparatus of claim 1 , wherein the switching circuit includes a first transistor and a second transistor connected together in series.

7. The apparatus of claim 6 , wherein the first and second transistors are configured to exhibit a leakage current via the current path that is less than 0.1 mA.

8. The apparatus of claim 1 , wherein the switching circuit includes three of more transistors connected together in series.

9. The apparatus of claim 1 , wherein in the second mode the switching circuit is configured and arranged to prevent negative voltage surges of up to 20V at the first node from reaching the second node.

10. The apparatus of claim 1 , further comprising a surge protection circuit including the switching and biasing circuits.

11. A mobile device, comprising:
a USB port having a power pin connected to the first node;
a battery coupled to the second node; and
a circuit protection circuit of claim 10 .

12. A method, comprising:
in a first mode,
enabling a current path between a first node and a second node by setting a control node of a switching circuit electrically connected in the current path to a first voltage;

in a second mode,
disabling the current path between the first node and the second node by setting the control node to a second voltage; and
in response to a voltage surge at the first node, preventing the switching circuit from enabling the current path to the second node by using a biasing circuit for biasing the voltage of the control node; and

wherein the switching circuit is configured to
operate in the first mode in response to a voltage of the control node relative to a voltage of the first node exceeding a threshold voltage, and
operate in the second mode in response to the voltage of the control node relative to the voltage of the first node being less than the threshold voltage,
wherein in the second mode the switching circuit is configured and arranged to disable the current path; and
the biasing circuit configured to, in the second mode, prevent a negative surge at the first node from enabling the current path to the second node by biasing the control node to reduce the voltage of the control node.

13. The method of claim 12 , wherein
the switching circuit includes at least one n-type transistor having a source and a drain electrically connected in the current path and a gate electrically connected to the control node,
the n-type transistor being configured to enable the current path in response to a gate-source voltage exceeding a threshold voltage and disable the current path in response to the gate-source voltage falling below the threshold voltage; and
the biasing of the voltage of the control node includes reducing the voltage of the control node by an amount sufficient to prevent a gate-source voltage from exceeding the threshold voltage.

14. The method of claim 12 , wherein the biasing of the voltage is performed using an n-type transistor having
a drain electrically connected to the control node,
a source electrically connected to the first node, and
a gate electrically connected to a ground voltage.

15. The method of claim 12 , further comprising,
operating in the second mode in response to a device including the switching circuit being powered on; and
in response to detecting connection of a power supply to the first node
determining whether voltage surge is present at the first node, and
operating in the first mode after determining that voltage surge is not present at the first node.

16. The method of claim 15 , further comprising,
while operating in the first mode, charging a battery connected to the second node by providing current from the first node to the second node via the current path.

17. The method of claim 15 , further comprising,
operating in the second mode in response to detecting a voltage surge while operating in the first mode.

18. The method of claim 15 , further comprising,
while operating in the first mode, communicating data between the first node and the second node.

19. The method of claim 15 , wherein
the switching circuit includes a first transistor and a second transistor coupled together in series in the current path; and
the first and second transistors are configured to exhibit a leakage current via the current path that is less than 0.1 mA.

Assignees

• Nxp Bv

Inventors

• Wang Ge

Classifications

• H02H9/046 Primary

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H02H11/006

  in case of too high or too low voltage · CPC title

• H01L27/0266

  Electricity · mapped topic

• H10D89/811 Primary

  using FETs as protective elements · CPC title