Semiconductor device

Patent metadata

Field	Value
Publication number	US-10164170-B2
Application number	US-201715622064-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Dec 6, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a plurality of lower conductive patterns stacked vertically on the substrate to be vertically spaced apart from each other at a first distance;
a magnetic tunnel junction stacked vertically on an uppermost lower conductive pattern of the plurality of lower conductive patterns;
an upper conductive line provided on the magnetic tunnel junction;
a bottom electrode contact between the magnetic tunnel junction and an uppermost lower conductive pattern of the plurality of lower conductive patterns; and
a top electrode between the magnetic tunnel junction and the upper conductive line,
wherein the upper conductive line is in direct contact with the top electrode,
wherein the bottom electrode contact is in direct contact with the uppermost lower conductive pattern,
wherein the uppermost lower conductive pattern has a first thickness and a first width,
wherein the upper conductive line has a second thickness larger than the first thickness of the uppermost lower conductive pattern and a second width larger than the first width of the uppermost lower conductive pattern, and
wherein a second distance between the upper conductive line and the uppermost lower conductive pattern is larger than the first distance.

2. The semiconductor device of claim 1 ,
wherein the second thickness is about two times the first thickness.

3. The semiconductor device of claim 1 ,
wherein the second distance is equal to or larger than about two times the first distance.

4. The semiconductor device of claim 1 ,
wherein each of the plurality of lower conductive patterns has substantially the same thickness.

5. The semiconductor device of claim 1 ,
wherein the substrate includes an active portion, and
wherein the semiconductor device further comprises:
a pair of word lines on the active portion of the substrate;
a first impurity region provided in the active portion of the substrate and between one of the pair of word lines and the other of the pair of word lines; and
second impurity regions provided in the active portion of the substrate and outside the pair of word lines,

wherein the magnetic tunnel junction is electrically connected to one of the second impurity regions through the plurality of lower conductive patterns.

6. The semiconductor device of claim 5 , further comprising:
a lower conductive line having a top surface located at substantially the same height as a top surface of one of the plurality of lower conductive patterns from the substrate,
wherein the lower conductive line is electrically connected to the first impurity region.

7. The semiconductor device of claim 6 ,
wherein a thickness of the lower conductive line is less than the second thickness, and
wherein a width of the lower conductive line is less than the second width.

8. The semiconductor device of claim 1 ,
wherein the substrate comprises a first region and a second region, and
wherein the magnetic tunnel junction is provided on the first region,
wherein the semiconductor device further comprises:
a first lower interconnection line provided on the substrate of the second region,
the first lower interconnection line having a top surface that is located at substantially the same height as a top surface of the uppermost lower conductive pattern; and
an upper interconnection line provided on the first lower interconnection line,

wherein a thickness of the first lower interconnection line is substantially the same as the first thickness of the uppermost lower conductive pattern, and
wherein a thickness of the upper interconnection line is substantially the same as the second thickness of the upper conductive line.

9. The semiconductor device of claim 8 ,
wherein a third distance between the first lower interconnection line and the upper interconnection line is larger than the first distance and is less than the second distance.

10. The semiconductor device of claim 9 ,
wherein the third distance is about two times the first distance.

11. The semiconductor device of claim 8 ,
wherein the semiconductor device further comprises:
a second lower interconnection line provided below the first lower interconnection line;
a first peripheral via plug provided between the upper interconnection line and the first lower interconnection line; and
a second peripheral via plug provided between the first lower interconnection line and the second lower interconnection line,
wherein the first peripheral via plug has a diameter larger than a diameter of the second peripheral via plug.

12. The semiconductor device of claim 11 ,
wherein a height of the first peripheral via plug is larger than a height of the second peripheral via plug.

13. The semiconductor device of claim 12 ,
wherein the height of the first peripheral via plug is about two times the height of the second peripheral via plug.

14. The semiconductor device of claim 1 ,
wherein an entire upper surface of the top electrode is in direct contact with the upper conductive line.

15. A semiconductor device, comprising:
a substrate including a first region and a second region;
a first lower conductive pattern and a first lower interconnection line provided on the first region and the second region, respectively, the first lower conductive pattern and the first lower interconnection line having top surfaces located at substantially the same height from the substrate;
an upper conductive line and an upper interconnection line provided on the first lower conductive pattern and the first lower interconnection line, respectively;
a magnetic tunnel junction provided between the first lower conductive pattern and the upper conductive line;
a bottom electrode contact between the magnetic tunnel junction and the first lower conductive pattern,
wherein an upper surface of the upper conductive line is higher than an upper surface of the upper interconnection line from the substrate,
wherein the magnetic tunnel junction, the bottom electrode contact and the first lower conductive pattern are vertically aligned; and
a first peripheral via plug provided between the lower first interconnection line and the upper interconnection line,
wherein thicknesses of the upper conductive line and the upper interconnection line are larger than thicknesses of the first lower conductive pattern and the first lower interconnection line, and
wherein widths of the upper conductive line and the upper interconnection line are larger than widths of the first lower conductive pattern and the first lower interconnection line.

16. The semiconductor device of claim 15 ,
wherein a distance between the first lower conductive pattern and the upper conductive line is larger than a distance between the first lower interconnection line and the upper interconnection line.

17. The semiconductor device of claim 16 ,
wherein the semiconductor device further comprises:
a second lower conductive pattern provided below the first lower conductive pattern; and
a second lower interconnection line provided below the first lower interconnection line,
wherein the second lower conductive pattern and the second lower interconnection line have top surfaces located at substantially the same height from the substrate, and
wherein a distance between the first lower interconnection line and the second lower interconnection line is less than the distance between the first lower interconnection line and the upper interconnection line.

18. The semiconductor device of claim 17

Assignees

• Suh Kiseok
• Bae Byoungjae
• Koh Gwanhyeob
• Song Yoonjong
• Lee Kilho
• Samsung Electronics Co Ltd

Inventors

• Suh Kiseok
• Bae Byoungjae
• Koh Gwanhyeob
• Song Yoonjong
• Lee Kilho

Classifications

• H01L43/02 Primary

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H10N50/80 Primary

  Constructional details · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title