Semiconductor device

Patent metadata

Field	Value
Publication number	US-10163850-B2
Application number	US-201715707632-A
Country	US
Kind code	B2
Filing date	Sep 18, 2017
Priority date	Jun 18, 2009
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

First claim

What is claimed is:

1. A semiconductor device comprising:
an interlayer insulating film formed on a semiconductor substrate;
an uppermost layer wiring made of copper and formed on the interlayer insulating film;
a lower layer wiring covered by the interlayer insulating film;
a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; and
a bonding wire made of copper and bonded directly to the electrode pad, wherein
the uppermost layer wiring includes a first portion laterally extending on the interlayer insulating film and a second portion integrally formed with the first portion such that the second portion is embedded in the interlayer insulating film, and
the lower layer wiring is electrically connected to the electrode pad via a pathway including the second portion of the uppermost layer wiring.

2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.

3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.

4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.

5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.

6. The semiconductor device according to claim 1 , wherein the second portion of the uppermost wiring layer includes a plurality of the second portions regularly arranged in a plan view.

7. The semiconductor device according to claim 1 , wherein the electrode pad is connected to the second portion of the uppermost layer wiring by the pathway being a geometric conductive pattern in a plan view.

8. The semiconductor device according to claim 1 , wherein
the pathway includes a first pathway, a second pathway and a third pathway between the second portion of the uppermost layer wiring and the electrode pad,
the first pathway extends along a first direction in a plan view,
the second pathway extends along a second direction in a plan view, and
the third pathway extends along a third direction in a plan view.

9. The semiconductor device according to claim 1 , wherein the pathway includes a conductive pattern having a linear shape in a plan view.

10. The semiconductor device according to claim 1 , wherein the pathway includes a conductive pattern having a planar shape in a plan view.

11. The semiconductor device according to claim 1 , wherein the pathway includes a conductive pattern having both a linear shape and a planar shape in a plan view.

Assignees

• Rohm Co Ltd

Inventors

• Haga Motoharu
• Yoshida Shingo
• Kasuya Yasumasa
• Nagahara Toichi
• Kimura Akihiro
• Fujii Kenji

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title