Apparatus and method of three dimensional conductive lines

Patent metadata

Field	Value
Publication number	US-10163759-B2
Application number	US-201815983786-A
Country	US
Kind code	B2
Filing date	May 18, 2018
Priority date	Nov 12, 2013
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

First claim

What is claimed is:

1. An inter-tier memory column, comprising:
a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC), said first segment comprising a first bit line comprising a first bit line part disposed along a first axis and a second bit line part connected to said first part and horizontally offset from said first axis;
a second segment disposed within a second tier of said 3D IC, comprising a second bit line comprising a third bit line part disposed along a second axis and a fourth bit line part connected to said third bit line part and disposed perpendicular to said second axis; and
wherein said first bit line is electrically connected to said second bit line by a conductive member extending continuously from said first bit line to said second bit line.

2. The inter-tier memory column of claim 1 , wherein said first segment and said second segment are aligned parallel to each other.

3. The inter-tier memory column of claim 1 , further comprising an inter-tier word line connected across said first segment and said second segment.

4. The inter-tier memory column of claim 1 , wherein said conductive member extends continuously from said second bit line part of said first bit line to said fourth bit line part of said second bit line.

5. The inter-tier memory column of claim 1 , comprising:
a first bit line bar disposed in a first tier of the 3D IC, the first bit line bar comprising a first bit line bar part and a horizontally offset second bit line bar part; and
a second bit line bar disposed in a second tier of the 3D IC, the second bit line bar comprising a third bit line bar part and a perpendicular fourth bit line bar part; and
wherein said horizontally offset second bit line bar part and said perpendicular fourth bit line bar part are connected by a vertical bit line.

6. The inter-tier memory column of claim 1 , further comprising:
a third segment disposed within said first tier of said 3D IC, said third segment comprising a third bit line comprising a fifth bit line part disposed along a third axis and a sixth bit line part connected to said fifth bit line part and horizontally offset from said third axis; and
a fourth segment disposed within said second tier of said 3D IC, comprising a fourth bit line comprising a seventh bit line part disposed along a fourth axis and an eighth bit line part connected to said seventh bit line part and disposed perpendicular to said fourth axis.

7. The inter-tier memory column of claim 6 , wherein said third bit line is electrically connected to said fourth bit line by a conductive member extending continuously from said third bit line to said fourth bit line.

8. The inter-tier memory column of claim 6 wherein said third segment is disposed above said second segment and said fourth segment is disposed below said first segment.

9. The inter-tier memory column of claim 1 , comprising a first conductive extender coupling said first bit line part to said second bit line part.

10. The inter-tier memory column of claim 9 , wherein said first coupling extender is disposed perpendicular to said first axis.

11. An inter-tier memory column, comprising:
a first segment disposed within a first tier of a three-dimensional integrated circuit (3D IC), said first segment comprising a first bit line comprising a first bit line part disposed along a first axis and a second bit line part connected to said first part and horizontally offset from said first axis, and a first plurality of memory cells electrically connected to said first bit line;
a second segment disposed within a second tier of said 3D IC, comprising a second bit line comprising a third bit line part disposed along a second axis and a fourth bit line part connected to said third part and disposed perpendicular to said second axis, and a second plurality of memory cells electrically connected to said second bit line;
wherein said horizontally offset second bit line part is connected to said perpendicular fourth bit line part by a first vertical conductive member.

12. The inter-tier memory column of claim 11 , comprising
a first bit line bar comprising a first bit line bar part and a horizontally offset second bit line bar part disposed in the first segment; and
a second bit line bar comprising a third bit line bar part and a perpendicular fourth bit line bar part disposed in the second segment;
wherein said horizontally offset second bit line bar part and said perpendicular fourth bit line bar part are connected by a second vertical conductive member.

13. The inter-tier memory column of claim 12 , wherein said second vertical conductive member extends continuously from said horizontally offset second bit line bar part to said perpendicular fourth bit line bar part.

14. The inter-tier memory column of claim 11 , comprising a first extender coupling said first bit line part and said horizontally offset second bit line part.

15. The inter-tier memory column of claim 13 , wherein the first extender is disposed perpendicular to the first axis.

16. The inter-tier memory column of claim 11 , wherein said first vertical conductive member extends continuously from said horizontally offset second bit line part to said perpendicular fourth bit line part.

17. A method of forming an inter-tier memory column, comprising:
forming a first segment in a first tier of a three-dimensional integrated circuit (3D IC), said first segment comprising a first bit line comprising a first bit line part disposed along a first axis and a second bit line part connected to said first part and horizontally offset from said first axis;
forming a second segment disposed within a second tier of the 3D IC, said second segment comprising a second segment disposed within a second tier of said 3D IC, comprising a second bit line comprising a third bit line part disposed along a second axis and a fourth bit line part connected to said third part and disposed perpendicular to said second axis; and
connecting said horizontally offset second bit line part to said perpendicular fourth bit line part with a first vertical conductive element.

18. The method of claim 17 , wherein said first vertical conductive element extends continuously from said horizontally offset second bit line part to said perpendicular fourth bit line part.

19. The method of claim 17 further comprising:
forming a first bit line bar in said first segment, said first bit line bar comprising a first bit line bar part disposed along a third axis parallel to the first axis and a second bit line bar part horizontally offset from said third axis;
forming a second bit line bar in said first segment, said second bit line bar comprising a third bit line bar part disposed along a fourth axis parallel to the second axis and a fourth bit line bar part disposed perpendicular to said fourth axis; and
connecting said first bit line bar to said second bit line bar with a second vertical conductive element.

20. The method of claim 17 , further comprising forming an inter-tier word line which connects at least one bit line of the first tier and at least one bit line of the second tier.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chih-Yu
• Lin Kao-Cheng
• Wang Li-Wen
• Chen Yen-Huei

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H01L25/0657

  Electricity · mapped topic